dcount8.v

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

//------------------------------------------------------------------------------
//
// File : dcount8.v
// Last Modification: 06/26/2001
//
// Created In SpDE Version: SpDE 8.22
// Author :	Richard Yuan, QuickLogic Corporation
// Copyright (C) 2001, Licensed Customers of QuickLogic may copy and modify
// this file for use in designing with QuickLogic devices only.
//	
// Description :
//	This file implements an 8-bit down counter converted from schematic.
//	 
// Hierarchy:
//	This file is to be included by dmacntrl.v.
//
// History:	
//	Date	        Author					Version
//	06/26/01		Richard Yuan			1.0
//		- Header added to conform to coding standard.
//
//------------------------------------------------------------------------------


`timescale 1ns/1ns  
`define LOGIC   1 
`define BIDIR   2 
`define INCELL  3 
`define CLOCK   4 
`define HSCK    5 
`define CLOCKB  6 

module dcount8( CLK, CLR, D, EN, LOAD, Q );
input CLK, CLR;
 input [7:0] D;
input EN, LOAD;
 output [7:0] Q;
wire N_5;
supply1 vcc;

dcntx4c I5 ( .CLK(CLK), .CLR(CLR), .D({ D[7:4] }), .ENG(EN), .ENP(vcc), .ENT(N_5),
          .LOAD(LOAD), .Q({ Q[7:4] }) );
dcntx4b I4 ( .CLK(CLK), .CLR(CLR), .D({ D[3:0] }), .ENG(EN), .ENP(vcc), .ENT(vcc),
          .LOAD(LOAD), .Q({ Q[3:0] }), .RCO(N_5) );

endmodule // dcount8


`ifdef dcntx4c
`else
`define dcntx4c
module dcntx4c( CLK, CLR, D, ENG, ENP, ENT, LOAD, Q );
input CLK, CLR;
 input [3:0] D;
input ENG, ENP, ENT, LOAD;
 output [3:0] Q;
supply0 GND;

dnfxbit QL4 ( .CLK(CLK), .CLR(CLR), .D(D[3]), .ENG(ENG), .ENP(ENP), .ENT(ENT),
           .LOAD(LOAD), .Q(Q[3]), .Q0(Q[0]), .Q1(Q[1]), .Q2(Q[2]) );
dnfxbit QL3 ( .CLK(CLK), .CLR(CLR), .D(D[2]), .ENG(ENG), .ENP(ENP), .ENT(ENT),
           .LOAD(LOAD), .Q(Q[2]), .Q0(Q[0]), .Q1(Q[1]), .Q2(GND) );
dnfxbit QL2 ( .CLK(CLK), .CLR(CLR), .D(D[1]), .ENG(ENG), .ENP(ENP), .ENT(ENT),
           .LOAD(LOAD), .Q(Q[1]), .Q0(Q[0]), .Q1(GND), .Q2(GND) );
dnfxbit QL1 ( .CLK(CLK), .CLR(CLR), .D(D[0]), .ENG(ENG), .ENP(ENP), .ENT(ENT),
           .LOAD(LOAD), .Q(Q[0]), .Q0(GND), .Q1(GND), .Q2(GND) );

endmodule // dcntx4c

`endif

`ifdef dcntx4b
`else
`define dcntx4b
module dcntx4b( CLK, CLR, D, ENG, ENP, ENT, LOAD, Q, RCO );
input CLK, CLR;
 input [3:0] D;
input ENG, ENP, ENT, LOAD;
 output [3:0] Q;
output RCO;
supply0 GND;

and5i4 QL5 ( .A(ENT), .B(Q[0]), .C(Q[1]), .D(Q[2]), .E(Q[3]), .Q(RCO) );
dnfxbit QL4 ( .CLK(CLK), .CLR(CLR), .D(D[3]), .ENG(ENG), .ENP(ENP), .ENT(ENT),
           .LOAD(LOAD), .Q(Q[3]), .Q0(Q[0]), .Q1(Q[1]), .Q2(Q[2]) );
dnfxbit QL3 ( .CLK(CLK), .CLR(CLR), .D(D[2]), .ENG(ENG), .ENP(ENP), .ENT(ENT),
           .LOAD(LOAD), .Q(Q[2]), .Q0(Q[0]), .Q1(Q[1]), .Q2(GND) );
dnfxbit QL2 ( .CLK(CLK), .CLR(CLR), .D(D[1]), .ENG(ENG), .ENP(ENP), .ENT(ENT),
           .LOAD(LOAD), .Q(Q[1]), .Q0(Q[0]), .Q1(GND), .Q2(GND) );
dnfxbit QL1 ( .CLK(CLK), .CLR(CLR), .D(D[0]), .ENG(ENG), .ENP(ENP), .ENT(ENT),
           .LOAD(LOAD), .Q(Q[0]), .Q0(GND), .Q1(GND), .Q2(GND) );

endmodule // dcntx4b

`endif

`ifdef dnfxbit
`else
`define dnfxbit
module dnfxbit( CLK, CLR, D, ENG, ENP, ENT, LOAD, Q, Q0, Q1, Q2 );
input CLK, CLR, D, ENG, ENP, ENT, LOAD;
output Q;
input Q0, Q1, Q2;
parameter ql_gate = `LOGIC;
wire N_1;
wire N_2;
wire N_3;
supply0 GND;
supply1 VCC;

frag_q I_3 ( .QC(CLK), .QD(N_1), .QR(CLR), .QS(GND), .QZ(Q) );
frag_m I_2 ( .B1(Q), .B2(GND), .C1(VCC), .C2(Q), .D1(D), .D2(GND), .E1(D), .E2(GND),
          .NS(N_2), .OS(N_3), .OZ(N_1) );
frag_f I_1 ( .F1(ENP), .F2(Q0), .F3(ENT), .F4(Q1), .F5(ENG), .F6(Q2), .FZ(N_2) );
frag_a QL1 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(GND), .A5(LOAD), .A6(GND), .AZ(N_3) );

endmodule // dnfxbit

`endif

`ifdef and5i4
`else
`define and5i4
module and5i4( A, B, C, D, E, Q );
input A, B, C, D, E;
output Q;
parameter ql_gate = `LOGIC;
wire N_1;
supply1 VCC;
supply0 GND;
wire N_2;

frag_f I_2 ( .F1(A), .F2(C), .F3(VCC), .F4(D), .F5(VCC), .F6(E), .FZ(N_1) );
frag_m I_1 ( .B1(VCC), .B2(GND), .C1(VCC), .C2(GND), .D1(GND), .D2(VCC), .E1(VCC),
          .E2(B), .NS(N_1), .NZ(Q), .OS(N_2) );
frag_a QL3 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND), .AZ(N_2) );

endmodule // and5i4

`endif

`ifdef frag_q
`else
`define frag_q
module frag_q( QC, QD, QR, QS, QZ );
input QC, QD, QR, QS;
output QZ;
parameter ql_frag = 1;
 reg QZ;
//`ifdef synthesis
 always @ (posedge QC or posedge QR or posedge QS) 
     if (QR)
        #1 QZ = 1'b0;
     else if (QS)
        #1 QZ = 1'b1;
     else #1 QZ = QD;
/* synopsys translate_off */
//`else
  always @ (QR or QS) begin
      if (QR)
         #1 assign QZ = 1'b0;
      else if (QS)
         #1 assign QZ = 1'b1;
      else
         #1 deassign QZ;
  end
  always @ (posedge QC)
         QZ = #1 QD;
  initial begin
    #1;
    if (QR)
         #1 assign QZ = 1'b0;
    else if (QS)
         #1 assign QZ = 1'b1;
  end
// `endif
/* synopsys translate_on */
endmodule // frag_q

`endif

`ifdef frag_m
`else
`define frag_m
module frag_m( B1, B2, C1, C2, D1, D2, E1, E2, NS, NZ, OS, OZ );
input B1, B2, C1, C2, D1, D2, E1, E2, NS;
output NZ;
input OS;
output OZ;
parameter ql_frag = 1;
 assign #1 NZ = NS ? (E1 & ~E2):(D1 & ~D2);
 assign #1 OZ = OS ? NZ:(NS ? (C1 & ~C2):(B1 & ~B2));

endmodule // frag_m

`endif

`ifdef frag_f
`else
`define frag_f
module frag_f( F1, F2, F3, F4, F5, F6, FZ );
input F1, F2, F3, F4, F5, F6;
output FZ;
parameter ql_frag = 1;
 assign #1 FZ = F1 & ~F2 & F3 & ~F4 & F5 & ~F6;

endmodule // frag_f

`endif

`ifdef frag_a
`else
`define frag_a
module frag_a( A1, A2, A3, A4, A5, A6, AZ );
input A1, A2, A3, A4, A5, A6;
output AZ;
parameter ql_frag = 1;
 assign #1 AZ = A1 & ~A2 & A3 & ~A4 & A5 & ~A6;

endmodule // frag_a

`endif