cfgtaddr_cardbus.v

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

assign #1 Lat_Gnt_IntPin_IntLine = {MaxLat[7:0], MinGnt[7:0], IntPin[7:0], IntLine[7:0]};


// *** assignments for the write-able registers and bits

// Status register, offset 04h

wire StatusRegWE = (IncrAddr & Cfg_Write & (cfgadr == 4'h1) & !CBE[3]);

always @(posedge PCI_clock or posedge PCI_reset) begin
	if (PCI_reset) begin
		ParErrorDetected <= 0;
		SignaledSystemError <= 0;
		ReceivedMasterAbort <= 0;
		ReceivedTargetAbort <= 0;
		// uncomment the following block for designs that are capable of generating target aborts
		// SignaledTargetAbort <= 0;
		DataParErrorDetected <= 0;
	end
	else begin
		casex ({PERR_Det,(WrData[31]&StatusRegWE)})
		  2'bx1: ParErrorDetected <= 1'b0;
		  2'b10: ParErrorDetected <= 1'b1;
		endcase

		casex ({SERR_Sig,(WrData[30]&StatusRegWE)})
		  2'bx1: SignaledSystemError <= 1'b0;
		  2'b10: SignaledSystemError <= 1'b1;
		endcase
		
		casex ({TTO_Det,(WrData[29]&StatusRegWE)})
		  2'bx1: ReceivedMasterAbort <= 1'b0;
		  2'b10: if (~MstSC) ReceivedMasterAbort <= 1'b1;
		endcase

		casex ({Tabort_Det,(WrData[28]&StatusRegWE)})
		  2'bx1: ReceivedTargetAbort <= 1'b0;
		  2'b10: ReceivedTargetAbort <= 1'b1;
		endcase

		// uncomment the following block for designs that are capable of generating target aborts
		// Usr_Abort is the signal connected to the Usr_Abort port of the PCI core
//		casex ({Usr_Abort,(WrData[27]&StatusRegWE)})
//		  2'bx1: SignaledTargetAbort <= 1'b0;
//		  2'b10: SignaledTargetAbort <= 1'b1;
//		endcase

		casex ({MstPERR_Det,(WrData[24]&StatusRegWE)})
		  2'bx1: DataParErrorDetected <= 1'b0;
		  2'b10: DataParErrorDetected <= 1'b1;
		endcase
	end
end


// Command register, offset 04h

wire CommandLoWE = (IncrAddr & Cfg_Write & (cfgadr == 4'h1) & !CBE[0]); 
wire CommandHiWE = (IncrAddr & Cfg_Write & (cfgadr == 4'h1) & !CBE[1]); 
 
always @(posedge PCI_clock or posedge PCI_reset) begin
	if (PCI_reset) begin
		MemEnable <= 0;
		BusMasterEnable <= 0;
		SpecialCycleEnable <= 0;
		MemWrAndInvalidateEnable <= 0;
		ParityErrorEnable <= 0;
	end
	else if (CommandLoWE) begin
		MemEnable <= WrData[1];
		BusMasterEnable <= WrData[2];
		SpecialCycleEnable <= WrData[3];
		MemWrAndInvalidateEnable <= WrData[4];
		ParityErrorEnable <= WrData[6];
	end
end

always @(posedge PCI_clock or posedge PCI_reset) begin
	if (PCI_reset)
		SERREnable <= 0;
	else if (CommandHiWE)
		SERREnable <= WrData[8];
end


// Latency Timer, offset 0Ch

wire LatTimerWE = (IncrAddr & Cfg_Write & !CBE[1] & (cfgadr==4'h3));

always @(posedge PCI_clock or posedge PCI_reset) begin
	if (PCI_reset)
		LatTimer[7:0] <= 8'h00;
	else if (LatTimerWE)
		LatTimer[7:0] <= WrData[15:8];
end
		

// Cache Line Size, offset 0Ch

wire CacheLineSizeWE = (IncrAddr & Cfg_Write & !CBE[0] & (cfgadr==4'h3));

always @(posedge PCI_clock or posedge PCI_reset) begin
	if (PCI_reset)
		CacheLineSize[7:2] <= 6'h00;
	else if (CacheLineSizeWE)
		CacheLineSize[7:2] <= WrData[7:2];
end


// Base Address Register 0, offset 10h

wire BAR0WE = (IncrAddr & Cfg_Write & (cfgadr==4'h4));

always @(posedge PCI_clock or posedge PCI_reset) begin
	if (PCI_reset)
	   //	BAR0_reg <= 22'hFFFFFF;
	   	BAR0_reg <= 0;
	else begin
		if (BAR0WE && !CBE[3]) BAR0_reg[31:24] <= WrData[31:24];
		if (BAR0WE && !CBE[2]) BAR0_reg[23:16] <= WrData[23:16];
		if (BAR0WE && !CBE[1]) BAR0_reg[15:10] <= WrData[15:10];
	end
end

// DS for CIS  BAR5, offset 24h
wire BAR5WE = (IncrAddr & Cfg_Write & (cfgadr==4'h9));

always @(posedge PCI_clock or posedge PCI_reset) begin
	if (PCI_reset)
	  //	BAR5_reg <= 22'hFFFFFF;
	   	BAR5_reg <= 0;
	else begin
		if (BAR5WE && !CBE[3]) BAR5_reg[31:24] <= WrData[31:24];
		if (BAR5WE && !CBE[2]) BAR5_reg[23:16] <= WrData[23:16];
		if (BAR5WE && !CBE[1]) BAR5_reg[15:10] <= WrData[15:10];
	end
end


// Interrupt Line, offset 3Ch
// Remove the following Comments for Interrupt Support

//wire IntLineWE = (IncrAddr & Cfg_Write & !CBE[0] & (cfgadr==4'hF));
//
//always @(posedge PCI_clock or posedge PCI_reset) begin
//	if (PCI_reset)
//	   IntLine <= 8'h00;
//	else if (IntLineWE)
//	   IntLine <= WrData[7:0];
//end


// Configuration Space Output Mux

always @(UsrAddr[8:2]) begin
	if (UsrAddr[8:6] == 3'b000)
		cfgadr <= UsrAddr[5:2];
	else
		cfgadr <= 4'b1110;  // Assign to a reserved address (38h)if not in a legal address range
							// This saves logic and assures that the read results in zeros
end

always @(cfgadr or Dev_Vend or Stat_Cmd or Class_RevID or BIST_Hdr_Lat_Cache or BAR0 or 
		 Cardbus_CIS or SubsysID_SubsysVendID or Expansion_ROM or Lat_Gnt_IntPin_IntLine
		 or BAR5)
	begin
		case (cfgadr)
			4'b0000: CfgData <= Dev_Vend;			 // allocated in CardBus
			4'b0001: CfgData <= Stat_Cmd;
			4'b0010: CfgData <= Class_RevID;		 // allocated in CardBus
			4'b0011: CfgData <= BIST_Hdr_Lat_Cache;
			4'b0100: CfgData <= BAR0;
			4'b1001: CfgData <= BAR5;				// DS for CIS
			4'b1010: CfgData <= Cardbus_CIS;
			4'b1011: CfgData <= SubsysID_SubsysVendID;// allocated in CardBus
			4'b1100: CfgData <= Expansion_ROM;
			4'b1111: CfgData <= Lat_Gnt_IntPin_IntLine;// all but IntPin allocated in CardBus
			default: CfgData <= 32'h0;
		endcase
end


// *** assignments to output ports
assign CmdReg = Stat_Cmd[15:0];
assign LatTimerReg = LatTimer;
assign CacheLineSizeReg = CacheLineSize;


// *****************************************
// ***  target address register/counter  ***
// *****************************************

always @(posedge PCI_clock or posedge PCI_reset)
	if (PCI_reset)
		UsrAddr[BAR0_size-1:0] <= #1 0;
	else if (LoadAddr) 
		UsrAddr[BAR0_size-1:0] <= #1 WrData[BAR0_size-1:0];
	else if (IncrAddr) begin
		UsrAddr[BAR0_size-1:2] <= #1 UsrAddr[BAR0_size-1:2] + 1;
		UsrAddr[1:0] <= #1 UsrAddr[1:0];
	end


assign	BAR0_Hit_int = (MemEnable && (WrData[31:BAR0_size] == BAR0_reg));
assign	BAR5_Hit_int = (MemEnable && (WrData[31:BAR5_size] == BAR5_reg));	// DS for CIS
assign	BAR0_Hit = BAR0_Hit_int;
assign	BAR5_Hit = BAR5_Hit_int;
assign	Addr_Hit = BAR0_Hit_int	|| BAR5_Hit_int;	// DS added

always @(posedge PCI_clock or posedge PCI_reset)
	if (PCI_reset)
		Usr_Stop <= 0;
	else
		Usr_Stop <= IncrAddr && (~(UsrAddr[1:0] == 2'b00) || (UsrAddr[BAR0_size-1:2] == {BAR0_size-2{1'b1}}));

// ************************
// ***  command decode  ***
// ************************

// map usr_read to mem read (0110), mem read mult (1100), or mem read line (1110)
assign Usr_RdCmd = ((CBE[2:0] == 3'b110) || ({CBE[3:2],CBE[0]} == {3'b110}));

// map usr_write to mem write (0111) and mem write and invalidate (1111)
assign Usr_WrCmd = (CBE[2:0] == 3'b111);


endmodule