cardbus_5632.rpt

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

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| Design Information |
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Design:            CARDBUS_5632
SpDE Version:      SpDE 9.5.4 Internal Build1
Report Generated:  Thu Apr 08 11:18:24 2004
CHIP Last Updated: Fri Feb 06 15:37:40 2004
Part Type:         ql5632-33
Speed Grade:       B
Operating Range:   Commercial
Package Type:      280 PIN PBGA
ESP Version :      pci32_25um v1_2
Link Check Sum: Undetermined: sequencer has not yet been run

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| Utilization Information |
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Utilized cells (preplacement):                 544 of     772  (70.5%)
Utilized cells (postplacement):                681 of     772  (88.2%)
Utilized Logic cell Frags (preplacement):     2466 of    4632  (53.2%)
Utilized Logic cell Frags (postplacement):    2751 of    4632  (59.4%)
Utilized Fragment A :                          551
Utilized Fragment F :                          540
Utilized Fragment O :                          565
Utilized Fragment N :                          622
IO control cells:                                0 of      16  (0.0%)
Clock only cells:                                1 of       8  (12.5%)
Bi directional cells:                          106 of     115  (92.2%)
RAM cells:                                       9 of      18  (50.0%)
ECU cells:                                       0 of      10  (0.0%)
PLL cells:                                       0 of       4  (0.0%)
Flip-Flop of IO cells:                          36 of     115  (31.3%)
1st Flip-Flop of Logic cells:                  203 of     772  (26.3%)
2nd Flip-Flop of Logic cells:                  270 of     772  (35.0%)
Routing resources:                           26026 of   78139  (33.3%)
ViaLink resources:                           22924 of 2096022  (1.1%)



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| Clock Network Utilization by clock pads |
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	Clock Network                  Net                                  Pin      Quad                  Load    
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	PLLMUX_BR2                     local_clock                          V11      Bottom Right           44      
	PLLMUX_TR2                     local_clock                          V11      Top Right              39      


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| Clock Network Utilization by Internal Logic |
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	Clock Network                  Net                                  Driver   Quad                  Load    
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	HSCKMUX_TR7                    N_20                                 V4       Top Right              34      
	HSCKMUX_BL7                    PCI_reset                            N5       Bottom Left            111     
	HSCKMUX_BR7                    N_20                                 V4       Bottom Right           35      
	HSCKMUX_TL6                    PCI_reset                            N5       Top Left               43      
	HSCKMUX_TR6                    N_19                                 V4       Top Right              20      
	HSCKMUX_BR6                    N_19                                 V4       Bottom Right           13      
	HSCKMUX_TR0                    fpga_oe_LRBUF944                     AJ11     Top Right              18      
	HSCKMUX_BR0                    fpga_oe_LRBUF944                     AJ11     Bottom Right           14      
	HSCKMUX_TR1                    PCI_reset                            N5       Top Right              87      
	HSCKMUX_BR1                    PCI_reset                            N5       Bottom Right           94      


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| Clock Network Utilization by PLL |
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|Available HSCK Clock Networks|
	Quad TOP LEFT     : 	3 of 4 QuadNets available	(75.0%)
	Quad TOP RIGHT    : 	1 of 5 QuadNets available	(20.0%)
	Quad BOTTOM LEFT  : 	4 of 5 QuadNets available	(80.0%)
	Quad BOTTOM RIGHT : 	1 of 5 QuadNets available	(20.0%)




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| Timing Results |
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Summary:

Longest Pad to Pad: 6.0 ns (pad_intr -- pad_CINT_n)

Clock                               Frequency       Setup Time      Clock to Out   
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CLK (ESP: PCI_clock)             40 MHz / 25.1 ns      8.3 ns         20.0 ns
lclk                            102 MHz /  9.8 ns      2.9 ns         10.6 ns


Inter Clock Domain Delay Matrix
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Clock0 = CLK 
Clock1 = lclk 

 
          Clock0    Clock1  
Clock0   25.1 ns   18.2 ns
Clock1    7.3 ns    9.8 ns

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| Tools run on design CARDBUS_5632 |
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partdef         6.0    
design          3.0    
logic optimizer 9.54    Mode = Quality Goal = Speed IgnorePack = FALSE UseNonBondedPads = TRUE Run Time 0:01:25
placer          9.54    Seed = 42 Mode = Quality Run Time 0:29:09
router          9.54    Seed = 42 Run Time 0:01:54
delay modeler   9.54    Mode = Commercial Corner = Worst SpeedGrade = B LowPower = FALSE Run Time 0:00:29
back annotation 9.54    Run Time 0:01:50
verifier        9.54    Strip = TRUE RemoveBuffersOnLoad = TRUE
auto buffer     9.54   


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| Pin Table |
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Display Pin Info option is FALSE.
Pin information will not be displayed.

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| Fixed Flip Flops |
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None


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| Fixed RAM cells |
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None


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| Fixed ECU cells |
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None


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| Nets Removed by Technology Mapper |
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Removed Nets option is FALSE.
Removed Nets information will not be displayed.



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