byte_enable_test.tf

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

//------------------------------------------------------------------------------
//
// File : byte_enable_test.tf
// Last Modification: 06/26/2001
//
// Created In SpDE Version: SpDE 8.22
// Author :	Richard Yuan, QuickLogic Corporation
// Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
// this file for use in designing with QuickLogic devices only.
//	
// Description :
//	This file tests the fully-customizable byte enable generation capability
//	of QL5332-33/QL5432-33 devices in their reference designs.
//	 
// Hierarchy:
//	This file is to be included by pci5(3/4)32_28.tf.
//
// History:	
//	Date	        Author					Version
//	06/26/01		Richard Yuan			1.0
//		- Header added to conform to coding standard.
//
//------------------------------------------------------------------------------


$display("\nStart of Byte Enable test, %0d",$time);

// write 3 dwords to configuration space to set up the master
master_2.data_array[0] = 32'h00000006;
master_2.data_array[1] = 32'h00000000;
master_2.data_array[2] = 32'h00004000;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h4,32'h0,CONFIG_WRITE,8'hFF,1'b0,1'b0,3,1,1,1'b0); 



$display("Generating a Master Read of 4 Using Byte Enables of 1,2,4,8", $time);
$display("\tTerminated by Mst_Two_Reads and Mst_One_Read");
// Write 4 byte enables into the BE fifo
master_2.data_array[0] = 32'h00000001;
master_2.data_array[1] = 32'h00000002;
master_2.data_array[2] = 32'h00000004;
master_2.data_array[3] = 32'h00000008;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;
master_2.be_array[3] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h22000200,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,4,1,1,1'b0);

// Setup a DMA read of 4
// Set Mst_Rd_Term_Sel low so it is terminated by Mst_Two_Reads and Mst_One_Read
CurRxSize = 4;
CurTxSize = CurRxSize;
DMARxTxCntReg = {CurTxSize, CurRxSize};
DMACtrlReg = {8'b11_0000_01, 8'b0_1_0000_00, 16'h0000};

// write the DMA setup data to the DMA control registers in the master
master_2.data_array[0] = DMARxTxCntReg;
master_2.data_array[1] = CurRxAddr;
master_2.data_array[2] = CurTxAddr;
master_2.data_array[3] = DMACtrlReg;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;
master_2.be_array[3] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,4,1,1,1'b0); 
repeat (30) @(posedge CLK);



$display("Generating a Master Read of 4 Using Byte Enables of 1,2,4,8", $time);
$display("\tTerminated by FIFO Empty Condition");
// Write 4 byte enables into the BE fifo
master_2.data_array[0] = 32'h00000001;
master_2.data_array[1] = 32'h00000002;
master_2.data_array[2] = 32'h00000004;
master_2.data_array[3] = 32'h00000008;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;
master_2.be_array[3] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h22000200,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,4,1,1,1'b0);

// Setup a DMA read of 4
// Set Mst_Rd_Term_Sel high so it is terminated by internal FIFO empty
// Mst_Two_Reads and Mst_One_Read signals are ignored by the core
CurRxSize = 4;
CurTxSize = CurRxSize;
DMARxTxCntReg = {CurTxSize, CurRxSize};
DMACtrlReg = {8'b11_0000_01, 8'b1_1_0000_00, 16'h0000};

// write the DMA setup data to the DMA control registers in the master
master_2.data_array[0] = DMARxTxCntReg;
master_2.data_array[1] = CurRxAddr;
master_2.data_array[2] = CurTxAddr;
master_2.data_array[3] = DMACtrlReg;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;
master_2.be_array[3] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,4,1,1,1'b0); 
repeat (30) @(posedge CLK);



$display("Generating a Master Write of 8 Using Byte Enables of 1,2,4,8,1,2,4,8", $time);
// Write 8 byte enables into the BE fifo
master_2.data_array[0] = 32'h00000001;
master_2.data_array[1] = 32'h00000002;
master_2.data_array[2] = 32'h00000004;
master_2.data_array[3] = 32'h00000008;
master_2.data_array[4] = 32'h00000001;
master_2.data_array[5] = 32'h00000002;
master_2.data_array[6] = 32'h00000004;
master_2.data_array[7] = 32'h00000008;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;
master_2.be_array[3] = 8'hFF;
master_2.be_array[4] = 8'hFF;
master_2.be_array[5] = 8'hFF;
master_2.be_array[6] = 8'hFF;
master_2.be_array[7] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h22000200,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,8,1,1,1'b0);


// Setup a DMA write of 8
CurRxSize = 8;
CurTxSize = CurRxSize;
DMARxTxCntReg = {CurTxSize, CurRxSize};
DMACtrlReg = {16'h4000, 8'b00_1_000_01, 8'h00};

// write the DMA setup data to the DMA control registers in the master
master_2.data_array[0] = DMARxTxCntReg;
master_2.data_array[1] = CurRxAddr;
master_2.data_array[2] = CurTxAddr;
master_2.data_array[3] = DMACtrlReg;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;
master_2.be_array[3] = 8'hFF;

// Start the DMA write to use those BEs
repeat (5) @(posedge CLK);
master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,4,1,1,1'b0); 
repeat (100) @(posedge CLK);


$display("Byte Enable test completed !  %0d\n",$time);