r64x4.v

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· Verilog 代码 · 共 38 行

`ifdef r64x4
`else
`define r64x4
`include "d:/pasic/spde/data/ram64x18.v"
/************************************************************************
** File : r64x4.v
** Design Date: June 9, 1998
** Creation Date: Thu Sep 21 17:00:30 2000

** Created By SpDE Version: SpDE 8.2 
** Author: Robert Maul, QuickLogic Corporation,
** Copyright (C) 1998, Customers of QuickLogic may copy and modify this
** file for use in designing QuickLogic devices only.
** Description : This file is autogenerated RTL code that describes the
** connectivity of cascaded RAM blocks (RAM banks) using QuickLogic's
** RAM block resources.
************************************************************************/

module r64x4(wa,ra,wd,rd,we,re,wclk,rclk);

// inputs: =wa[5:0]=,=ra[5:0]=,=wd[3:0]=,we,re,wclk,rclk
// outputs: =rd[3:0]=

input re;
input rclk;
input we;
input wclk;
input [5:0] wa;
input [5:0] ra;
input [3:0] wd;
output [3:0] rd;
supply0 GND;
supply1 VCC;
RAM64X18 r64x4I1 (.WA(wa),.RA(ra),.WD({wd[3],wd[2],wd[1],wd[0], GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}),.RD({rd[3],rd[2],rd[1],rd[0], dummy0, dummy1, dummy2, dummy3, dummy4, dummy5, dummy6, dummy7, dummy8, dummy9, dummy10, dummy11, dummy12, dummy13}),
  .WE(we),.RE(re),.WCLK(wclk),.RCLK(rclk),.ASYNCRD(GND));
endmodule
`endif