f64x4.v

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

`timescale 1ns/1ns
`ifdef f64x4
`else
`define f64x4
`include "r64x4.v"
`include "ucnt6.v"
`include "updcnt6.v"
/************************************************************************
** File : f64x4.v
** Date : Jan. 14, 1998
** Creation Date: Thu Sep 21 17:00:30 2000
** Created By SpDE Version: SpDE 8.2 
** Authors : Brian Faith, John Birkner, Brian Small, Mike Dini
** Copyright (C) 1998, Customers of QuickLogic may copy and modify this
** file for use in designing QuickLogic devices only.
** Description : This file is autogenerated RTL code that describes the
** control logic to implement a FIFO using QuickLogic's RAM resources
** and core logic cells.
************************************************************************/

module f64x4 (pop, push, din, dout, emptyn, fulln, clk, rst);

// inputs: =din[3:0]=,pop,push,clk,rst
// outputs: =dout[3:0]=,emptyn,fulln

input pop, push, clk, rst;
input [3:0] din;
output emptyn, fulln;
output [3:0] dout;
wire wr_enable, rd_enable, rd_status_enable;
reg emptyn, fulln, init_read;
wire [5:0] wr_addr, rd_addr, status_addr;

/* Generate enable lines for the address counters */
assign #1 wr_enable = push & fulln;  /* If push command and FIFO is not full */
assign #1 rd_enable = (pop & emptyn) | init_read; /* If pop command and FIFO is not empty */
assign #1 rd_status_enable = (pop & emptyn);

/* Instantiate the counters for the addresses */
ucnt6 ucnt6I1 (.rst(rst), .enable(wr_enable), .clk(clk), .q(wr_addr));
ucnt6 ucnt6I2 (.rst(rst), .enable(rd_enable), .clk(clk), .q(rd_addr));

/* Instantiate the RAM block for FIFO */
r64x4 r64x4I1 (.wa(wr_addr), .ra(rd_addr), .wd(din), .rd(dout), 
              .we(wr_enable), .re(rd_enable), .wclk(clk), .rclk(clk));

/* Instantiate the Up Down counter for keeping track of empty or full */
updcnt6 updcnt6I1 (.rst(rst), .up(wr_enable), .down(rd_status_enable),
         .clk(clk), .q(status_addr));

/* Check for positive edge of system clock */
always @(posedge rst or posedge clk) begin
   if (rst) begin
      init_read <= #1 1'b1;
      fulln <= #1 1'b1;
      emptyn <= #1 1'b0;
   end else begin
      /* clear the init_read on the first clock after a reset */
      /* init_read is needed to sychronize the RAM read address on reset */
      init_read <= #1 1'b0;
      /* calculate full flag */
      if (((status_addr == 6'b111111) & push & ~pop) | 
          (~fulln & !pop))
         fulln <= #1 1'b0;
      else
         fulln <= #1 1'b1;
      /* calculate empty flag */
      if (((status_addr == 6'b000001) & pop & ~push) |
          (~emptyn & !push))
         emptyn <= #1 1'b0;
      else
         emptyn <= #1 1'b1;
   end
 /* if */
end /* always */
endmodule /* f64x4 */
`endif