zhishi.vhd

VHDL语言设计的秒表

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY zhishi IS
	PORT(
		clk1, reset: IN	STD_LOGIC;
		msec: IN	STD_LOGIC_VECTOR(7 downto 0);
		sec : IN	STD_LOGIC_VECTOR(6 downto 0);
		minute : in std_logic_vector (6 downto 0);
		daout	: OUT	STD_LOGIC_vector (3 downto 0);
		sel : out std_logic_vector ( 2 downto 0));
END zhishi;
ARCHITECTURE fun OF zhishi IS
	SIGNAL count: STD_LOGIC_vector ( 2 downto 0);--?
BEGIN
    sel <= count;
    process ( clk1,reset)
       begin 
           if (reset ='0') then
              count <= "000";
           elsif (clk1 'event and clk1='1') then
               if ( count >= "101") then
                    count <= "000";
               else 
                    count <= count + 1;
               end if;
           end if;
    case count is
    when "000" => daout <= msec(3 downto 0);--
    when "001" => daout<=msec (7 downto 4);
    when "010" => daout <= sec (3 downto 0);
    when "011" => daout(3) <= '0';
              daout(2 downto 0) <= sec (6 downto 4);
    when "100" => daout <= minute (3 downto 0);
    when others => daout(3) <= '0';
                   daout(2 downto 0) <= minute(6 downto 4);
    end case;
    end process;
end fun;