second.tan.rpt

VHDL语言设计的秒表

; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[6]   ; count[1]   ; clk        ; clk      ; None                        ; None                      ; 2.438 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[6]   ; count[0]   ; clk        ; clk      ; None                        ; None                      ; 2.438 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[5]   ; enmin~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.343 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[4]   ; enmin~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.261 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1]   ; enmin~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.206 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[6]   ; enmin~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.187 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; enmin~reg0 ; enmin~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.116 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[2]   ; enmin~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.049 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[3]   ; enmin~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.914 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0]   ; enmin~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.724 ns                ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------+
; tsu                                                                ;
+-------+--------------+------------+--------+------------+----------+
; Slack ; Required tsu ; Actual tsu ; From   ; To         ; To Clock ;
+-------+--------------+------------+--------+------------+----------+
; N/A   ; None         ; -0.008 ns  ; setsec ; enmin~reg0 ; clk      ;
; N/A   ; None         ; -0.072 ns  ; reset  ; enmin~reg0 ; clk      ;
; N/A   ; None         ; -0.848 ns  ; setsec ; count[0]   ; clk      ;
; N/A   ; None         ; -0.848 ns  ; setsec ; count[1]   ; clk      ;
; N/A   ; None         ; -0.848 ns  ; setsec ; count[2]   ; clk      ;
; N/A   ; None         ; -0.848 ns  ; setsec ; count[3]   ; clk      ;
; N/A   ; None         ; -0.848 ns  ; setsec ; count[5]   ; clk      ;
; N/A   ; None         ; -0.848 ns  ; setsec ; count[4]   ; clk      ;
; N/A   ; None         ; -0.848 ns  ; setsec ; count[6]   ; clk      ;
+-------+--------------+------------+--------+------------+----------+


+------------------------------------------------------------------------+
; tco                                                                    ;
+-------+--------------+------------+------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From       ; To       ; From Clock ;
+-------+--------------+------------+------------+----------+------------+
; N/A   ; None         ; 12.242 ns  ; count[4]   ; daout[4] ; clk        ;
; N/A   ; None         ; 12.237 ns  ; count[5]   ; daout[5] ; clk        ;
; N/A   ; None         ; 12.226 ns  ; count[6]   ; daout[6] ; clk        ;
; N/A   ; None         ; 12.212 ns  ; count[1]   ; daout[1] ; clk        ;
; N/A   ; None         ; 12.210 ns  ; count[3]   ; daout[3] ; clk        ;
; N/A   ; None         ; 12.208 ns  ; count[2]   ; daout[2] ; clk        ;
; N/A   ; None         ; 12.171 ns  ; enmin~reg0 ; enmin    ; clk        ;
; N/A   ; None         ; 11.770 ns  ; count[0]   ; daout[0] ; clk        ;
+-------+--------------+------------+------------+----------+------------+


+--------------------------------------------------------------------------+
; th                                                                       ;
+---------------+-------------+-----------+--------+------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To         ; To Clock ;
+---------------+-------------+-----------+--------+------------+----------+
; N/A           ; None        ; 0.900 ns  ; setsec ; count[0]   ; clk      ;
; N/A           ; None        ; 0.900 ns  ; setsec ; count[1]   ; clk      ;
; N/A           ; None        ; 0.900 ns  ; setsec ; count[2]   ; clk      ;
; N/A           ; None        ; 0.900 ns  ; setsec ; count[3]   ; clk      ;
; N/A           ; None        ; 0.900 ns  ; setsec ; count[5]   ; clk      ;
; N/A           ; None        ; 0.900 ns  ; setsec ; count[4]   ; clk      ;
; N/A           ; None        ; 0.900 ns  ; setsec ; count[6]   ; clk      ;
; N/A           ; None        ; 0.124 ns  ; reset  ; enmin~reg0 ; clk      ;
; N/A           ; None        ; 0.060 ns  ; setsec ; enmin~reg0 ; clk      ;
+---------------+-------------+-----------+--------+------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Mon Jun 16 10:07:15 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off second -c second --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 271.15 MHz between source register "count[1]" and destination register "count[6]" (period= 3.688 ns)
    Info: + Longest register to register delay is 3.427 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y24_N2; Fanout = 5; REG Node = 'count[1]'
        Info: 2: + IC(0.551 ns) + CELL(0.590 ns) = 1.141 ns; Loc. = LC_X1_Y24_N0; Fanout = 8; COMB Node = 'rtl~45'
        Info: 3: + IC(0.705 ns) + CELL(0.564 ns) = 2.410 ns; Loc. = LC_X1_Y24_N3; Fanout = 2; COMB Node = 'count[2]~308'
        Info: 4: + IC(0.000 ns) + CELL(0.178 ns) = 2.588 ns; Loc. = LC_X1_Y24_N4; Fanout = 3; COMB Node = 'count[3]~312'
        Info: 5: + IC(0.000 ns) + CELL(0.839 ns) = 3.427 ns; Loc. = LC_X1_Y24_N7; Fanout = 4; REG Node = 'count[6]'
        Info: Total cell delay = 2.171 ns ( 63.35 % )
        Info: Total interconnect delay = 1.256 ns ( 36.65 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 8.278 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 8; CLK Node = 'clk'
            Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y24_N7; Fanout = 4; REG Node = 'count[6]'
            Info: Total cell delay = 2.180 ns ( 26.33 % )
            Info: Total interconnect delay = 6.098 ns ( 73.67 % )
        Info: - Longest clock path from clock "clk" to source register is 8.278 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 8; CLK Node = 'clk'
            Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y24_N2; Fanout = 5; REG Node = 'count[1]'
            Info: Total cell delay = 2.180 ns ( 26.33 % )
            Info: Total interconnect delay = 6.098 ns ( 73.67 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "enmin~reg0" (data pin = "setsec", clock pin = "clk") is -0.008 ns
    Info: + Longest pin to register delay is 8.233 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_6; Fanout = 8; PIN Node = 'setsec'
        Info: 2: + IC(4.977 ns) + CELL(0.590 ns) = 7.036 ns; Loc. = LC_X2_Y24_N2; Fanout = 1; COMB Node = 'enmin~206'
        Info: 3: + IC(0.719 ns) + CELL(0.478 ns) = 8.233 ns; Loc. = LC_X1_Y24_N9; Fanout = 4; REG Node = 'enmin~reg0'
        Info: Total cell delay = 2.537 ns ( 30.82 % )
        Info: Total interconnect delay = 5.696 ns ( 69.18 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 8.278 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y24_N9; Fanout = 4; REG Node = 'enmin~reg0'
        Info: Total cell delay = 2.180 ns ( 26.33 % )
        Info: Total interconnect delay = 6.098 ns ( 73.67 % )
Info: tco from clock "clk" to destination pin "daout[4]" through register "count[4]" is 12.242 ns
    Info: + Longest clock path from clock "clk" to source register is 8.278 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y24_N5; Fanout = 6; REG Node = 'count[4]'
        Info: Total cell delay = 2.180 ns ( 26.33 % )
        Info: Total interconnect delay = 6.098 ns ( 73.67 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.740 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y24_N5; Fanout = 6; REG Node = 'count[4]'
        Info: 2: + IC(1.616 ns) + CELL(2.124 ns) = 3.740 ns; Loc. = PIN_14; Fanout = 0; PIN Node = 'daout[4]'
        Info: Total cell delay = 2.124 ns ( 56.79 % )
        Info: Total interconnect delay = 1.616 ns ( 43.21 % )
Info: th for register "count[0]" (data pin = "setsec", clock pin = "clk") is 0.900 ns
    Info: + Longest clock path from clock "clk" to destination register is 8.278 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y24_N1; Fanout = 5; REG Node = 'count[0]'
        Info: Total cell delay = 2.180 ns ( 26.33 % )
        Info: Total interconnect delay = 6.098 ns ( 73.67 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.393 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_6; Fanout = 8; PIN Node = 'setsec'
        Info: 2: + IC(5.057 ns) + CELL(0.867 ns) = 7.393 ns; Loc. = LC_X1_Y24_N1; Fanout = 5; REG Node = 'count[0]'
        Info: Total cell delay = 2.336 ns ( 31.60 % )
        Info: Total interconnect delay = 5.057 ns ( 68.40 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Jun 16 10:07:15 2008
    Info: Elapsed time: 00:00:01