alert.hier_info

VHDL语言设计的秒表

|alert
clk => lamp[1]~reg0.CLK
clk => lamp[0]~reg0.CLK
clk => count[1].CLK
clk => count[0].CLK
clk => lamp[2]~reg0.CLK
dain[0] => ~NO_FANOUT~
dain[1] => ~NO_FANOUT~
dain[2] => ~NO_FANOUT~
dain[3] => ~NO_FANOUT~
dain[4] => ~NO_FANOUT~
dain[5] => ~NO_FANOUT~
dain[6] => ~NO_FANOUT~
lamp[0] <= lamp[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lamp[1] <= lamp[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lamp[2] <= lamp[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE