second.tan.qmsg

VHDL语言设计的秒表

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count\[1\] register count\[6\] 271.15 MHz 3.688 ns Internal " "Info: Clock \"clk\" has Internal fmax of 271.15 MHz between source register \"count\[1\]\" and destination register \"count\[6\]\" (period= 3.688 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.427 ns + Longest register register " "Info: + Longest register to register delay is 3.427 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LC_X1_Y24_N2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y24_N2; Fanout = 5; REG Node = 'count\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "" { count[1] } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.551 ns) + CELL(0.590 ns) 1.141 ns rtl~45 2 COMB LC_X1_Y24_N0 8 " "Info: 2: + IC(0.551 ns) + CELL(0.590 ns) = 1.141 ns; Loc. = LC_X1_Y24_N0; Fanout = 8; COMB Node = 'rtl~45'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "1.141 ns" { count[1] rtl~45 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.705 ns) + CELL(0.564 ns) 2.410 ns count\[2\]~308 3 COMB LC_X1_Y24_N3 2 " "Info: 3: + IC(0.705 ns) + CELL(0.564 ns) = 2.410 ns; Loc. = LC_X1_Y24_N3; Fanout = 2; COMB Node = 'count\[2\]~308'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "1.269 ns" { rtl~45 count[2]~308 } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 2.588 ns count\[3\]~312 4 COMB LC_X1_Y24_N4 3 " "Info: 4: + IC(0.000 ns) + CELL(0.178 ns) = 2.588 ns; Loc. = LC_X1_Y24_N4; Fanout = 3; COMB Node = 'count\[3\]~312'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "0.178 ns" { count[2]~308 count[3]~312 } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 3.427 ns count\[6\] 5 REG LC_X1_Y24_N7 4 " "Info: 5: + IC(0.000 ns) + CELL(0.839 ns) = 3.427 ns; Loc. = LC_X1_Y24_N7; Fanout = 4; REG Node = 'count\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "0.839 ns" { count[3]~312 count[6] } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.171 ns ( 63.35 % ) " "Info: Total cell delay = 2.171 ns ( 63.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.256 ns ( 36.65 % ) " "Info: Total interconnect delay = 1.256 ns ( 36.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "3.427 ns" { count[1] rtl~45 count[2]~308 count[3]~312 count[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.427 ns" { count[1] rtl~45 count[2]~308 count[3]~312 count[6] } { 0.000ns 0.551ns 0.705ns 0.000ns 0.000ns } { 0.000ns 0.590ns 0.564ns 0.178ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.278 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.278 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 8; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.098 ns) + CELL(0.711 ns) 8.278 ns count\[6\] 2 REG LC_X1_Y24_N7 4 " "Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y24_N7; Fanout = 4; REG Node = 'count\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "6.809 ns" { clk count[6] } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.33 % ) " "Info: Total cell delay = 2.180 ns ( 26.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.098 ns ( 73.67 % ) " "Info: Total interconnect delay = 6.098 ns ( 73.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "8.278 ns" { clk count[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[6] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.278 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.278 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 8; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.098 ns) + CELL(0.711 ns) 8.278 ns count\[1\] 2 REG LC_X1_Y24_N2 5 " "Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y24_N2; Fanout = 5; REG Node = 'count\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "6.809 ns" { clk count[1] } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.33 % ) " "Info: Total cell delay = 2.180 ns ( 26.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.098 ns ( 73.67 % ) " "Info: Total interconnect delay = 6.098 ns ( 73.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "8.278 ns" { clk count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[1] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "8.278 ns" { clk count[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[6] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "8.278 ns" { clk count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[1] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "3.427 ns" { count[1] rtl~45 count[2]~308 count[3]~312 count[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.427 ns" { count[1] rtl~45 count[2]~308 count[3]~312 count[6] } { 0.000ns 0.551ns 0.705ns 0.000ns 0.000ns } { 0.000ns 0.590ns 0.564ns 0.178ns 0.839ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "8.278 ns" { clk count[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[6] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "8.278 ns" { clk count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[1] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "enmin~reg0 setsec clk -0.008 ns register " "Info: tsu for register \"enmin~reg0\" (data pin = \"setsec\", clock pin = \"clk\") is -0.008 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.233 ns + Longest pin register " "Info: + Longest pin to register delay is 8.233 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns setsec 1 PIN PIN_6 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_6; Fanout = 8; PIN Node = 'setsec'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "" { setsec } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.977 ns) + CELL(0.590 ns) 7.036 ns enmin~206 2 COMB LC_X2_Y24_N2 1 " "Info: 2: + IC(4.977 ns) + CELL(0.590 ns) = 7.036 ns; Loc. = LC_X2_Y24_N2; Fanout = 1; COMB Node = 'enmin~206'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "5.567 ns" { setsec enmin~206 } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.719 ns) + CELL(0.478 ns) 8.233 ns enmin~reg0 3 REG LC_X1_Y24_N9 4 " "Info: 3: + IC(0.719 ns) + CELL(0.478 ns) = 8.233 ns; Loc. = LC_X1_Y24_N9; Fanout = 4; REG Node = 'enmin~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "1.197 ns" { enmin~206 enmin~reg0 } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.537 ns ( 30.82 % ) " "Info: Total cell delay = 2.537 ns ( 30.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.696 ns ( 69.18 % ) " "Info: Total interconnect delay = 5.696 ns ( 69.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "8.233 ns" { setsec enmin~206 enmin~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.233 ns" { setsec setsec~out0 enmin~206 enmin~reg0 } { 0.000ns 0.000ns 4.977ns 0.719ns } { 0.000ns 1.469ns 0.590ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.278 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.278 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 8; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.098 ns) + CELL(0.711 ns) 8.278 ns enmin~reg0 2 REG LC_X1_Y24_N9 4 " "Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y24_N9; Fanout = 4; REG Node = 'enmin~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "6.809 ns" { clk enmin~reg0 } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.33 % ) " "Info: Total cell delay = 2.180 ns ( 26.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.098 ns ( 73.67 % ) " "Info: Total interconnect delay = 6.098 ns ( 73.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "8.278 ns" { clk enmin~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 enmin~reg0 } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "8.233 ns" { setsec enmin~206 enmin~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.233 ns" { setsec setsec~out0 enmin~206 enmin~reg0 } { 0.000ns 0.000ns 4.977ns 0.719ns } { 0.000ns 1.469ns 0.590ns 0.478ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "8.278 ns" { clk enmin~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 enmin~reg0 } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk daout\[4\] count\[4\] 12.242 ns register " "Info: tco from clock \"clk\" to destination pin \"daout\[4\]\" through register \"count\[4\]\" is 12.242 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.278 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.278 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 8; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.098 ns) + CELL(0.711 ns) 8.278 ns count\[4\] 2 REG LC_X1_Y24_N5 6 " "Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y24_N5; Fanout = 6; REG Node = 'count\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "6.809 ns" { clk count[4] } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.33 % ) " "Info: Total cell delay = 2.180 ns ( 26.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.098 ns ( 73.67 % ) " "Info: Total interconnect delay = 6.098 ns ( 73.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "8.278 ns" { clk count[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[4] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.740 ns + Longest register pin " "Info: + Longest register to pin delay is 3.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[4\] 1 REG LC_X1_Y24_N5 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y24_N5; Fanout = 6; REG Node = 'count\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "" { count[4] } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.616 ns) + CELL(2.124 ns) 3.740 ns daout\[4\] 2 PIN PIN_14 0 " "Info: 2: + IC(1.616 ns) + CELL(2.124 ns) = 3.740 ns; Loc. = PIN_14; Fanout = 0; PIN Node = 'daout\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "3.740 ns" { count[4] daout[4] } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 56.79 % ) " "Info: Total cell delay = 2.124 ns ( 56.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.616 ns ( 43.21 % ) " "Info: Total interconnect delay = 1.616 ns ( 43.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "3.740 ns" { count[4] daout[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.740 ns" { count[4] daout[4] } { 0.000ns 1.616ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "8.278 ns" { clk count[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[4] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "3.740 ns" { count[4] daout[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.740 ns" { count[4] daout[4] } { 0.000ns 1.616ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "count\[0\] setsec clk 0.900 ns register " "Info: th for register \"count\[0\]\" (data pin = \"setsec\", clock pin = \"clk\") is 0.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.278 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.278 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 8; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.098 ns) + CELL(0.711 ns) 8.278 ns count\[0\] 2 REG LC_X1_Y24_N1 5 " "Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y24_N1; Fanout = 5; REG Node = 'count\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "6.809 ns" { clk count[0] } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.33 % ) " "Info: Total cell delay = 2.180 ns ( 26.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.098 ns ( 73.67 % ) " "Info: Total interconnect delay = 6.098 ns ( 73.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "8.278 ns" { clk count[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[0] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.393 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.393 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns setsec 1 PIN PIN_6 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_6; Fanout = 8; PIN Node = 'setsec'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "" { setsec } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.057 ns) + CELL(0.867 ns) 7.393 ns count\[0\] 2 REG LC_X1_Y24_N1 5 " "Info: 2: + IC(5.057 ns) + CELL(0.867 ns) = 7.393 ns; Loc. = LC_X1_Y24_N1; Fanout = 5; REG Node = 'count\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "5.924 ns" { setsec count[0] } "NODE_NAME" } "" } } { "second.vhd" "" { Text "D:/miaobiao/second.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 31.60 % ) " "Info: Total cell delay = 2.336 ns ( 31.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.057 ns ( 68.40 % ) " "Info: Total interconnect delay = 5.057 ns ( 68.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "7.393 ns" { setsec count[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.393 ns" { setsec setsec~out0 count[0] } { 0.000ns 0.000ns 5.057ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "8.278 ns" { clk count[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[0] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "second" "UNKNOWN" "V1" "D:/miaobiao/db/second.quartus_db" { Floorplan "D:/miaobiao/" "" "7.393 ns" { setsec count[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.393 ns" { setsec setsec~out0 count[0] } { 0.000ns 0.000ns 5.057ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}