msecond.hier_info

VHDL语言设计的秒表

|msecond
clk => count[6].CLK
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => ensec~reg0.CLK
clk => count[7].CLK
reset => count[6].ACLR
reset => count[5].ACLR
reset => count[4].ACLR
reset => count[3].ACLR
reset => count[2].ACLR
reset => count[1].ACLR
reset => count[0].ACLR
reset => count[7].ACLR
setmsec => count[6].ENA
setmsec => count[5].ENA
setmsec => count[4].ENA
setmsec => count[3].ENA
setmsec => count[2].ENA
setmsec => count[1].ENA
setmsec => count[0].ENA
setmsec => count[7].ENA
ensec <= ensec~reg0.DB_MAX_OUTPUT_PORT_TYPE
daout[0] <= count[0].DB_MAX_OUTPUT_PORT_TYPE
daout[1] <= count[1].DB_MAX_OUTPUT_PORT_TYPE
daout[2] <= count[2].DB_MAX_OUTPUT_PORT_TYPE
daout[3] <= count[3].DB_MAX_OUTPUT_PORT_TYPE
daout[4] <= count[4].DB_MAX_OUTPUT_PORT_TYPE
daout[5] <= count[5].DB_MAX_OUTPUT_PORT_TYPE
daout[6] <= count[6].DB_MAX_OUTPUT_PORT_TYPE
daout[7] <= count[7].DB_MAX_OUTPUT_PORT_TYPE