minute.tan.qmsg

来自「VHDL语言设计的秒表」· QMSG 代码 · 共 10 行 · 第 1/3 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register count\[1\] count\[3\] 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"count\[1\]\" and destination register \"count\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.295 ns + Longest register register " "Info: + Longest register to register delay is 3.295 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LC_X1_Y23_N2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y23_N2; Fanout = 5; REG Node = 'count\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { count[1] } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.546 ns) + CELL(0.590 ns) 1.136 ns rtl~33 2 COMB LC_X1_Y23_N0 7 " "Info: 2: + IC(0.546 ns) + CELL(0.590 ns) = 1.136 ns; Loc. = LC_X1_Y23_N0; Fanout = 7; COMB Node = 'rtl~33'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.136 ns" { count[1] rtl~33 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.467 ns) + CELL(0.114 ns) 1.717 ns count\[0\]~297 3 COMB LC_X1_Y23_N8 7 " "Info: 3: + IC(0.467 ns) + CELL(0.114 ns) = 1.717 ns; Loc. = LC_X1_Y23_N8; Fanout = 7; COMB Node = 'count\[0\]~297'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.581 ns" { rtl~33 count[0]~297 } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.466 ns) + CELL(1.112 ns) 3.295 ns count\[3\] 4 REG LC_X1_Y23_N4 4 " "Info: 4: + IC(0.466 ns) + CELL(1.112 ns) = 3.295 ns; Loc. = LC_X1_Y23_N4; Fanout = 4; REG Node = 'count\[3\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.578 ns" { count[0]~297 count[3] } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.816 ns ( 55.11 % ) " "Info: Total cell delay = 1.816 ns ( 55.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.479 ns ( 44.89 % ) " "Info: Total interconnect delay = 1.479 ns ( 44.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.295 ns" { count[1] rtl~33 count[0]~297 count[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.295 ns" { count[1] rtl~33 count[0]~297 count[3] } { 0.000ns 0.546ns 0.467ns 0.466ns } { 0.000ns 0.590ns 0.114ns 1.112ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.278 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.278 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 7; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.098 ns) + CELL(0.711 ns) 8.278 ns count\[3\] 2 REG LC_X1_Y23_N4 4 " "Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y23_N4; Fanout = 4; REG Node = 'count\[3\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "6.809 ns" { clk count[3] } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.33 % ) " "Info: Total cell delay = 2.180 ns ( 26.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.098 ns ( 73.67 % ) " "Info: Total interconnect delay = 6.098 ns ( 73.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk count[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[3] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.278 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.278 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 7; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.098 ns) + CELL(0.711 ns) 8.278 ns count\[1\] 2 REG LC_X1_Y23_N2 5 " "Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y23_N2; Fanout = 5; REG Node = 'count\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "6.809 ns" { clk count[1] } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.33 % ) " "Info: Total cell delay = 2.180 ns ( 26.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.098 ns ( 73.67 % ) " "Info: Total interconnect delay = 6.098 ns ( 73.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk count[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[1] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk count[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[3] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk count[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[1] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.295 ns" { count[1] rtl~33 count[0]~297 count[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.295 ns" { count[1] rtl~33 count[0]~297 count[3] } { 0.000ns 0.546ns 0.467ns 0.466ns } { 0.000ns 0.590ns 0.114ns 1.112ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk count[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[3] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk count[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[1] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { count[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { count[3] } {  } {  } } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "count\[0\] setmin clk -0.800 ns register " "Info: tsu for register \"count\[0\]\" (data pin = \"setmin\", clock pin = \"clk\") is -0.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.441 ns + Longest pin register " "Info: + Longest pin to register delay is 7.441 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns setmin 1 PIN PIN_16 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 7; PIN Node = 'setmin'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { setmin } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.105 ns) + CELL(0.867 ns) 7.441 ns count\[0\] 2 REG LC_X1_Y23_N1 5 " "Info: 2: + IC(5.105 ns) + CELL(0.867 ns) = 7.441 ns; Loc. = LC_X1_Y23_N1; Fanout = 5; REG Node = 'count\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "5.972 ns" { setmin count[0] } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 31.39 % ) " "Info: Total cell delay = 2.336 ns ( 31.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.105 ns ( 68.61 % ) " "Info: Total interconnect delay = 5.105 ns ( 68.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "7.441 ns" { setmin count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.441 ns" { setmin setmin~out0 count[0] } { 0.000ns 0.000ns 5.105ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.278 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.278 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 7; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.098 ns) + CELL(0.711 ns) 8.278 ns count\[0\] 2 REG LC_X1_Y23_N1 5 " "Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y23_N1; Fanout = 5; REG Node = 'count\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "6.809 ns" { clk count[0] } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.33 % ) " "Info: Total cell delay = 2.180 ns ( 26.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.098 ns ( 73.67 % ) " "Info: Total interconnect delay = 6.098 ns ( 73.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[0] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "7.441 ns" { setmin count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.441 ns" { setmin setmin~out0 count[0] } { 0.000ns 0.000ns 5.105ns } { 0.000ns 1.469ns 0.867ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[0] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk daout\[2\] count\[2\] 12.231 ns register " "Info: tco from clock \"clk\" to destination pin \"daout\[2\]\" through register \"count\[2\]\" is 12.231 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.278 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.278 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 7; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.098 ns) + CELL(0.711 ns) 8.278 ns count\[2\] 2 REG LC_X1_Y23_N3 5 " "Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y23_N3; Fanout = 5; REG Node = 'count\[2\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "6.809 ns" { clk count[2] } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.33 % ) " "Info: Total cell delay = 2.180 ns ( 26.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.098 ns ( 73.67 % ) " "Info: Total interconnect delay = 6.098 ns ( 73.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk count[2] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[2] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.729 ns + Longest register pin " "Info: + Longest register to pin delay is 3.729 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[2\] 1 REG LC_X1_Y23_N3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y23_N3; Fanout = 5; REG Node = 'count\[2\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { count[2] } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.605 ns) + CELL(2.124 ns) 3.729 ns daout\[2\] 2 PIN PIN_7 0 " "Info: 2: + IC(1.605 ns) + CELL(2.124 ns) = 3.729 ns; Loc. = PIN_7; Fanout = 0; PIN Node = 'daout\[2\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.729 ns" { count[2] daout[2] } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 56.96 % ) " "Info: Total cell delay = 2.124 ns ( 56.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.605 ns ( 43.04 % ) " "Info: Total interconnect delay = 1.605 ns ( 43.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.729 ns" { count[2] daout[2] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.729 ns" { count[2] daout[2] } { 0.000ns 1.605ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk count[2] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[2] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.729 ns" { count[2] daout[2] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.729 ns" { count[2] daout[2] } { 0.000ns 1.605ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "count\[0\] setmin clk 0.852 ns register " "Info: th for register \"count\[0\]\" (data pin = \"setmin\", clock pin = \"clk\") is 0.852 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.278 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.278 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 7; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.098 ns) + CELL(0.711 ns) 8.278 ns count\[0\] 2 REG LC_X1_Y23_N1 5 " "Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y23_N1; Fanout = 5; REG Node = 'count\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "6.809 ns" { clk count[0] } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.33 % ) " "Info: Total cell delay = 2.180 ns ( 26.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.098 ns ( 73.67 % ) " "Info: Total interconnect delay = 6.098 ns ( 73.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[0] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.441 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.441 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns setmin 1 PIN PIN_16 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 7; PIN Node = 'setmin'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { setmin } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.105 ns) + CELL(0.867 ns) 7.441 ns count\[0\] 2 REG LC_X1_Y23_N1 5 " "Info: 2: + IC(5.105 ns) + CELL(0.867 ns) = 7.441 ns; Loc. = LC_X1_Y23_N1; Fanout = 5; REG Node = 'count\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "5.972 ns" { setmin count[0] } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 31.39 % ) " "Info: Total cell delay = 2.336 ns ( 31.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.105 ns ( 68.61 % ) " "Info: Total interconnect delay = 5.105 ns ( 68.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "7.441 ns" { setmin count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.441 ns" { setmin setmin~out0 count[0] } { 0.000ns 0.000ns 5.105ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 count[0] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "minute" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/minute.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "7.441 ns" { setmin count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.441 ns" { setmin setmin~out0 count[0] } { 0.000ns 0.000ns 5.105ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}