msecond.tan.qmsg

VHDL语言设计的秒表

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count\[1\] register count\[6\] 255.56 MHz 3.913 ns Internal " "Info: Clock \"clk\" has Internal fmax of 255.56 MHz between source register \"count\[1\]\" and destination register \"count\[6\]\" (period= 3.913 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.652 ns + Longest register register " "Info: + Longest register to register delay is 3.652 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LC_X1_Y23_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y23_N1; Fanout = 5; REG Node = 'count\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { count[1] } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.531 ns) + CELL(0.590 ns) 1.121 ns rtl~43 2 COMB LC_X1_Y23_N9 8 " "Info: 2: + IC(0.531 ns) + CELL(0.590 ns) = 1.121 ns; Loc. = LC_X1_Y23_N9; Fanout = 8; COMB Node = 'rtl~43'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.121 ns" { count[1] rtl~43 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.013 ns) + CELL(0.423 ns) 2.557 ns count\[2\]~343 3 COMB LC_X1_Y23_N2 2 " "Info: 3: + IC(1.013 ns) + CELL(0.423 ns) = 2.557 ns; Loc. = LC_X1_Y23_N2; Fanout = 2; COMB Node = 'count\[2\]~343'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.436 ns" { rtl~43 count[2]~343 } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 2.635 ns count\[3\]~347 4 COMB LC_X1_Y23_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 2.635 ns; Loc. = LC_X1_Y23_N3; Fanout = 2; COMB Node = 'count\[3\]~347'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.078 ns" { count[2]~343 count[3]~347 } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 2.813 ns count\[4\]~351 5 COMB LC_X1_Y23_N4 3 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 2.813 ns; Loc. = LC_X1_Y23_N4; Fanout = 3; COMB Node = 'count\[4\]~351'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.178 ns" { count[3]~347 count[4]~351 } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 3.652 ns count\[6\] 6 REG LC_X1_Y23_N6 6 " "Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 3.652 ns; Loc. = LC_X1_Y23_N6; Fanout = 6; REG Node = 'count\[6\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.839 ns" { count[4]~351 count[6] } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 57.72 % ) " "Info: Total cell delay = 2.108 ns ( 57.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.544 ns ( 42.28 % ) " "Info: Total interconnect delay = 1.544 ns ( 42.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.652 ns" { count[1] rtl~43 count[2]~343 count[3]~347 count[4]~351 count[6] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.652 ns" { count[1] rtl~43 count[2]~343 count[3]~347 count[4]~351 count[6] } { 0.000ns 0.531ns 1.013ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.590ns 0.423ns 0.078ns 0.178ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.290 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.290 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 9; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.110 ns) + CELL(0.711 ns) 8.290 ns count\[6\] 2 REG LC_X1_Y23_N6 6 " "Info: 2: + IC(6.110 ns) + CELL(0.711 ns) = 8.290 ns; Loc. = LC_X1_Y23_N6; Fanout = 6; REG Node = 'count\[6\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "6.821 ns" { clk count[6] } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.30 % ) " "Info: Total cell delay = 2.180 ns ( 26.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.110 ns ( 73.70 % ) " "Info: Total interconnect delay = 6.110 ns ( 73.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.290 ns" { clk count[6] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.290 ns" { clk clk~out0 count[6] } { 0.000ns 0.000ns 6.110ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.290 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.290 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 9; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.110 ns) + CELL(0.711 ns) 8.290 ns count\[1\] 2 REG LC_X1_Y23_N1 5 " "Info: 2: + IC(6.110 ns) + CELL(0.711 ns) = 8.290 ns; Loc. = LC_X1_Y23_N1; Fanout = 5; REG Node = 'count\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "6.821 ns" { clk count[1] } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.30 % ) " "Info: Total cell delay = 2.180 ns ( 26.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.110 ns ( 73.70 % ) " "Info: Total interconnect delay = 6.110 ns ( 73.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.290 ns" { clk count[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.290 ns" { clk clk~out0 count[1] } { 0.000ns 0.000ns 6.110ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.290 ns" { clk count[6] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.290 ns" { clk clk~out0 count[6] } { 0.000ns 0.000ns 6.110ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.290 ns" { clk count[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.290 ns" { clk clk~out0 count[1] } { 0.000ns 0.000ns 6.110ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.652 ns" { count[1] rtl~43 count[2]~343 count[3]~347 count[4]~351 count[6] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.652 ns" { count[1] rtl~43 count[2]~343 count[3]~347 count[4]~351 count[6] } { 0.000ns 0.531ns 1.013ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.590ns 0.423ns 0.078ns 0.178ns 0.839ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.290 ns" { clk count[6] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.290 ns" { clk clk~out0 count[6] } { 0.000ns 0.000ns 6.110ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.290 ns" { clk count[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.290 ns" { clk clk~out0 count[1] } { 0.000ns 0.000ns 6.110ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ensec~reg0 reset clk 0.223 ns register " "Info: tsu for register \"ensec~reg0\" (data pin = \"reset\", clock pin = \"clk\") is 0.223 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.476 ns + Longest pin register " "Info: + Longest pin to register delay is 8.476 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset 1 PIN PIN_3 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_3; Fanout = 9; PIN Node = 'reset'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { reset } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.410 ns) + CELL(0.590 ns) 7.469 ns ensec~263 2 COMB LC_X2_Y23_N5 1 " "Info: 2: + IC(5.410 ns) + CELL(0.590 ns) = 7.469 ns; Loc. = LC_X2_Y23_N5; Fanout = 1; COMB Node = 'ensec~263'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "6.000 ns" { reset ensec~263 } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.607 ns) 8.476 ns ensec~reg0 3 REG LC_X2_Y23_N4 2 " "Info: 3: + IC(0.400 ns) + CELL(0.607 ns) = 8.476 ns; Loc. = LC_X2_Y23_N4; Fanout = 2; REG Node = 'ensec~reg0'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.007 ns" { ensec~263 ensec~reg0 } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.666 ns ( 31.45 % ) " "Info: Total cell delay = 2.666 ns ( 31.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.810 ns ( 68.55 % ) " "Info: Total interconnect delay = 5.810 ns ( 68.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.476 ns" { reset ensec~263 ensec~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.476 ns" { reset reset~out0 ensec~263 ensec~reg0 } { 0.000ns 0.000ns 5.410ns 0.400ns } { 0.000ns 1.469ns 0.590ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.290 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.290 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 9; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.110 ns) + CELL(0.711 ns) 8.290 ns ensec~reg0 2 REG LC_X2_Y23_N4 2 " "Info: 2: + IC(6.110 ns) + CELL(0.711 ns) = 8.290 ns; Loc. = LC_X2_Y23_N4; Fanout = 2; REG Node = 'ensec~reg0'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "6.821 ns" { clk ensec~reg0 } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.30 % ) " "Info: Total cell delay = 2.180 ns ( 26.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.110 ns ( 73.70 % ) " "Info: Total interconnect delay = 6.110 ns ( 73.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.290 ns" { clk ensec~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.290 ns" { clk clk~out0 ensec~reg0 } { 0.000ns 0.000ns 6.110ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.476 ns" { reset ensec~263 ensec~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.476 ns" { reset reset~out0 ensec~263 ensec~reg0 } { 0.000ns 0.000ns 5.410ns 0.400ns } { 0.000ns 1.469ns 0.590ns 0.607ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.290 ns" { clk ensec~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.290 ns" { clk clk~out0 ensec~reg0 } { 0.000ns 0.000ns 6.110ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk ensec ensec~reg0 12.498 ns register " "Info: tco from clock \"clk\" to destination pin \"ensec\" through register \"ensec~reg0\" is 12.498 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.290 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.290 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 9; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.110 ns) + CELL(0.711 ns) 8.290 ns ensec~reg0 2 REG LC_X2_Y23_N4 2 " "Info: 2: + IC(6.110 ns) + CELL(0.711 ns) = 8.290 ns; Loc. = LC_X2_Y23_N4; Fanout = 2; REG Node = 'ensec~reg0'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "6.821 ns" { clk ensec~reg0 } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.30 % ) " "Info: Total cell delay = 2.180 ns ( 26.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.110 ns ( 73.70 % ) " "Info: Total interconnect delay = 6.110 ns ( 73.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.290 ns" { clk ensec~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.290 ns" { clk clk~out0 ensec~reg0 } { 0.000ns 0.000ns 6.110ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.984 ns + Longest register pin " "Info: + Longest register to pin delay is 3.984 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ensec~reg0 1 REG LC_X2_Y23_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y23_N4; Fanout = 2; REG Node = 'ensec~reg0'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { ensec~reg0 } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.860 ns) + CELL(2.124 ns) 3.984 ns ensec 2 PIN PIN_5 0 " "Info: 2: + IC(1.860 ns) + CELL(2.124 ns) = 3.984 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'ensec'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.984 ns" { ensec~reg0 ensec } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 53.31 % ) " "Info: Total cell delay = 2.124 ns ( 53.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.860 ns ( 46.69 % ) " "Info: Total interconnect delay = 1.860 ns ( 46.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.984 ns" { ensec~reg0 ensec } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.984 ns" { ensec~reg0 ensec } { 0.000ns 1.860ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.290 ns" { clk ensec~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.290 ns" { clk clk~out0 ensec~reg0 } { 0.000ns 0.000ns 6.110ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.984 ns" { ensec~reg0 ensec } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.984 ns" { ensec~reg0 ensec } { 0.000ns 1.860ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "count\[0\] setmsec clk 0.848 ns register " "Info: th for register \"count\[0\]\" (data pin = \"setmsec\", clock pin = \"clk\") is 0.848 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.290 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.290 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 9; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.110 ns) + CELL(0.711 ns) 8.290 ns count\[0\] 2 REG LC_X1_Y23_N0 5 " "Info: 2: + IC(6.110 ns) + CELL(0.711 ns) = 8.290 ns; Loc. = LC_X1_Y23_N0; Fanout = 5; REG Node = 'count\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "6.821 ns" { clk count[0] } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.30 % ) " "Info: Total cell delay = 2.180 ns ( 26.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.110 ns ( 73.70 % ) " "Info: Total interconnect delay = 6.110 ns ( 73.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.290 ns" { clk count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.290 ns" { clk clk~out0 count[0] } { 0.000ns 0.000ns 6.110ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.457 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.457 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns setmsec 1 PIN PIN_4 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_4; Fanout = 9; PIN Node = 'setmsec'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { setmsec } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.121 ns) + CELL(0.867 ns) 7.457 ns count\[0\] 2 REG LC_X1_Y23_N0 5 " "Info: 2: + IC(5.121 ns) + CELL(0.867 ns) = 7.457 ns; Loc. = LC_X1_Y23_N0; Fanout = 5; REG Node = 'count\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "5.988 ns" { setmsec count[0] } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 31.33 % ) " "Info: Total cell delay = 2.336 ns ( 31.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.121 ns ( 68.67 % ) " "Info: Total interconnect delay = 5.121 ns ( 68.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "7.457 ns" { setmsec count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.457 ns" { setmsec setmsec~out0 count[0] } { 0.000ns 0.000ns 5.121ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.290 ns" { clk count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.290 ns" { clk clk~out0 count[0] } { 0.000ns 0.000ns 6.110ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "msecond" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/msecond.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "7.457 ns" { setmsec count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.457 ns" { setmsec setmsec~out0 count[0] } { 0.000ns 0.000ns 5.121ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}