alert.tan.qmsg

VHDL语言设计的秒表

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register count\[0\] lamp\[2\]~reg0 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"count\[0\]\" and destination register \"lamp\[2\]~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.518 ns + Longest register register " "Info: + Longest register to register delay is 2.518 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[0\] 1 REG LC_X1_Y26_N6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y26_N6; Fanout = 5; REG Node = 'count\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { count[0] } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/alert.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.580 ns) + CELL(0.590 ns) 1.170 ns lamp\[0\]~133 2 COMB LC_X1_Y26_N9 2 " "Info: 2: + IC(0.580 ns) + CELL(0.590 ns) = 1.170 ns; Loc. = LC_X1_Y26_N9; Fanout = 2; COMB Node = 'lamp\[0\]~133'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.170 ns" { count[0] lamp[0]~133 } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/alert.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.481 ns) + CELL(0.867 ns) 2.518 ns lamp\[2\]~reg0 3 REG LC_X1_Y26_N8 1 " "Info: 3: + IC(0.481 ns) + CELL(0.867 ns) = 2.518 ns; Loc. = LC_X1_Y26_N8; Fanout = 1; REG Node = 'lamp\[2\]~reg0'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.348 ns" { lamp[0]~133 lamp[2]~reg0 } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/alert.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns ( 57.86 % ) " "Info: Total cell delay = 1.457 ns ( 57.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.061 ns ( 42.14 % ) " "Info: Total interconnect delay = 1.061 ns ( 42.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "2.518 ns" { count[0] lamp[0]~133 lamp[2]~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "2.518 ns" { count[0] lamp[0]~133 lamp[2]~reg0 } { 0.000ns 0.580ns 0.481ns } { 0.000ns 0.590ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.245 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/alert.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns lamp\[2\]~reg0 2 REG LC_X1_Y26_N8 1 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X1_Y26_N8; Fanout = 1; REG Node = 'lamp\[2\]~reg0'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.776 ns" { clk lamp[2]~reg0 } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/alert.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.245 ns" { clk lamp[2]~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 lamp[2]~reg0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.245 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/alert.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns count\[0\] 2 REG LC_X1_Y26_N6 5 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X1_Y26_N6; Fanout = 5; REG Node = 'count\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.776 ns" { clk count[0] } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/alert.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.245 ns" { clk count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 count[0] } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.245 ns" { clk lamp[2]~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 lamp[2]~reg0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.245 ns" { clk count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 count[0] } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "alert.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/alert.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "alert.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/alert.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "2.518 ns" { count[0] lamp[0]~133 lamp[2]~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "2.518 ns" { count[0] lamp[0]~133 lamp[2]~reg0 } { 0.000ns 0.580ns 0.481ns } { 0.000ns 0.590ns 0.867ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.245 ns" { clk lamp[2]~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 lamp[2]~reg0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.245 ns" { clk count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 count[0] } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { lamp[2]~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { lamp[2]~reg0 } {  } {  } } } { "alert.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/alert.vhd" 15 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk lamp\[0\] lamp\[0\]~reg0 7.173 ns register " "Info: tco from clock \"clk\" to destination pin \"lamp\[0\]\" through register \"lamp\[0\]~reg0\" is 7.173 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.245 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/alert.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns lamp\[0\]~reg0 2 REG LC_X1_Y26_N4 2 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X1_Y26_N4; Fanout = 2; REG Node = 'lamp\[0\]~reg0'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.776 ns" { clk lamp[0]~reg0 } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/alert.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.245 ns" { clk lamp[0]~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 lamp[0]~reg0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "alert.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/alert.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.704 ns + Longest register pin " "Info: + Longest register to pin delay is 3.704 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lamp\[0\]~reg0 1 REG LC_X1_Y26_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y26_N4; Fanout = 2; REG Node = 'lamp\[0\]~reg0'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { lamp[0]~reg0 } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/alert.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.580 ns) + CELL(2.124 ns) 3.704 ns lamp\[0\] 2 PIN PIN_3 0 " "Info: 2: + IC(1.580 ns) + CELL(2.124 ns) = 3.704 ns; Loc. = PIN_3; Fanout = 0; PIN Node = 'lamp\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.704 ns" { lamp[0]~reg0 lamp[0] } "NODE_NAME" } "" } } { "alert.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/alert.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 57.34 % ) " "Info: Total cell delay = 2.124 ns ( 57.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.580 ns ( 42.66 % ) " "Info: Total interconnect delay = 1.580 ns ( 42.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.704 ns" { lamp[0]~reg0 lamp[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.704 ns" { lamp[0]~reg0 lamp[0] } { 0.000ns 1.580ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.245 ns" { clk lamp[0]~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 lamp[0]~reg0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "alert" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/alert.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.704 ns" { lamp[0]~reg0 lamp[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.704 ns" { lamp[0]~reg0 lamp[0] } { 0.000ns 1.580ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 06 22:11:49 2008 " "Info: Processing ended: Fri Jun 06 22:11:49 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}