zhishi.hier_info

VHDL语言设计的秒表

|zhishi
clk1 => count[1].CLK
clk1 => count[0].CLK
clk1 => count[2].CLK
reset => count[1].ACLR
reset => count[0].ACLR
reset => count[2].ACLR
msec[0] => Mux~3.IN1
msec[1] => Mux~2.IN1
msec[2] => Mux~1.IN1
msec[3] => Mux~0.IN5
msec[4] => Mux~3.IN0
msec[5] => Mux~2.IN0
msec[6] => Mux~1.IN0
msec[7] => Mux~0.IN4
sec[0] => Mux~3.IN3
sec[1] => Mux~2.IN3
sec[2] => Mux~1.IN3
sec[3] => Mux~0.IN6
sec[4] => Mux~3.IN2
sec[5] => Mux~2.IN2
sec[6] => Mux~1.IN2
minute[0] => Mux~3.IN7
minute[1] => Mux~2.IN7
minute[2] => Mux~1.IN7
minute[3] => Mux~0.IN7
minute[4] => Mux~3.IN4
minute[4] => Mux~3.IN5
minute[4] => Mux~3.IN6
minute[5] => Mux~2.IN4
minute[5] => Mux~2.IN5
minute[5] => Mux~2.IN6
minute[6] => Mux~1.IN4
minute[6] => Mux~1.IN5
minute[6] => Mux~1.IN6
daout[0] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
daout[1] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
daout[2] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
daout[3] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE
sel[0] <= count[0].DB_MAX_OUTPUT_PORT_TYPE
sel[1] <= count[1].DB_MAX_OUTPUT_PORT_TYPE
sel[2] <= count[2].DB_MAX_OUTPUT_PORT_TYPE