zhishi.tan.qmsg

VHDL语言设计的秒表

{ "Info" "ITDB_FULL_TCO_RESULT" "clk1 daout\[1\] count\[0\] 10.151 ns register " "Info: tco from clock \"clk1\" to destination pin \"daout\[1\]\" through register \"count\[0\]\" is 10.151 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 3.245 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to source register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk1 1 CLK PIN_29 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 3; CLK Node = 'clk1'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhishi" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/zhishi.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk1 } "NODE_NAME" } "" } } { "zhishi.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/zhishi.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns count\[0\] 2 REG LC_X1_Y23_N6 13 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X1_Y23_N6; Fanout = 13; REG Node = 'count\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhishi" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/zhishi.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.776 ns" { clk1 count[0] } "NODE_NAME" } "" } } { "zhishi.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/zhishi.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhishi" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/zhishi.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.245 ns" { clk1 count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk1 clk1~out0 count[0] } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "zhishi.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/zhishi.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.682 ns + Longest register pin " "Info: + Longest register to pin delay is 6.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[0\] 1 REG LC_X1_Y23_N6 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y23_N6; Fanout = 13; REG Node = 'count\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhishi" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/zhishi.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { count[0] } "NODE_NAME" } "" } } { "zhishi.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/zhishi.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.676 ns) + CELL(0.442 ns) 2.118 ns Mux~966 2 COMB LC_X4_Y26_N8 1 " "Info: 2: + IC(1.676 ns) + CELL(0.442 ns) = 2.118 ns; Loc. = LC_X4_Y26_N8; Fanout = 1; COMB Node = 'Mux~966'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhishi" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/zhishi.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "2.118 ns" { count[0] Mux~966 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.447 ns) + CELL(0.292 ns) 2.857 ns Mux~967 3 COMB LC_X4_Y26_N6 1 " "Info: 3: + IC(0.447 ns) + CELL(0.292 ns) = 2.857 ns; Loc. = LC_X4_Y26_N6; Fanout = 1; COMB Node = 'Mux~967'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhishi" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/zhishi.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.739 ns" { Mux~966 Mux~967 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 3.153 ns Mux~968 4 COMB LC_X4_Y26_N7 1 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 3.153 ns; Loc. = LC_X4_Y26_N7; Fanout = 1; COMB Node = 'Mux~968'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhishi" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/zhishi.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.296 ns" { Mux~967 Mux~968 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.405 ns) + CELL(2.124 ns) 6.682 ns daout\[1\] 5 PIN PIN_1 0 " "Info: 5: + IC(1.405 ns) + CELL(2.124 ns) = 6.682 ns; Loc. = PIN_1; Fanout = 0; PIN Node = 'daout\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhishi" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/zhishi.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.529 ns" { Mux~968 daout[1] } "NODE_NAME" } "" } } { "zhishi.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/zhishi.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.972 ns ( 44.48 % ) " "Info: Total cell delay = 2.972 ns ( 44.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.710 ns ( 55.52 % ) " "Info: Total interconnect delay = 3.710 ns ( 55.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhishi" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/zhishi.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "6.682 ns" { count[0] Mux~966 Mux~967 Mux~968 daout[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.682 ns" { count[0] Mux~966 Mux~967 Mux~968 daout[1] } { 0.000ns 1.676ns 0.447ns 0.182ns 1.405ns } { 0.000ns 0.442ns 0.292ns 0.114ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhishi" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/zhishi.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.245 ns" { clk1 count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk1 clk1~out0 count[0] } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhishi" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/zhishi.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "6.682 ns" { count[0] Mux~966 Mux~967 Mux~968 daout[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "6.682 ns" { count[0] Mux~966 Mux~967 Mux~968 daout[1] } { 0.000ns 1.676ns 0.447ns 0.182ns 1.405ns } { 0.000ns 0.442ns 0.292ns 0.114ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "msec\[1\] daout\[1\] 12.373 ns Longest " "Info: Longest tpd from source pin \"msec\[1\]\" to destination pin \"daout\[1\]\" is 12.373 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns msec\[1\] 1 PIN PIN_225 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_225; Fanout = 1; PIN Node = 'msec\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhishi" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/zhishi.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { msec[1] } "NODE_NAME" } "" } } { "zhishi.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/zhishi.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.744 ns) + CELL(0.590 ns) 7.809 ns Mux~966 2 COMB LC_X4_Y26_N8 1 " "Info: 2: + IC(5.744 ns) + CELL(0.590 ns) = 7.809 ns; Loc. = LC_X4_Y26_N8; Fanout = 1; COMB Node = 'Mux~966'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhishi" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/zhishi.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "6.334 ns" { msec[1] Mux~966 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.447 ns) + CELL(0.292 ns) 8.548 ns Mux~967 3 COMB LC_X4_Y26_N6 1 " "Info: 3: + IC(0.447 ns) + CELL(0.292 ns) = 8.548 ns; Loc. = LC_X4_Y26_N6; Fanout = 1; COMB Node = 'Mux~967'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhishi" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/zhishi.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.739 ns" { Mux~966 Mux~967 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 8.844 ns Mux~968 4 COMB LC_X4_Y26_N7 1 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 8.844 ns; Loc. = LC_X4_Y26_N7; Fanout = 1; COMB Node = 'Mux~968'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhishi" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/zhishi.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.296 ns" { Mux~967 Mux~968 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.405 ns) + CELL(2.124 ns) 12.373 ns daout\[1\] 5 PIN PIN_1 0 " "Info: 5: + IC(1.405 ns) + CELL(2.124 ns) = 12.373 ns; Loc. = PIN_1; Fanout = 0; PIN Node = 'daout\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhishi" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/zhishi.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.529 ns" { Mux~968 daout[1] } "NODE_NAME" } "" } } { "zhishi.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/zhishi.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.595 ns ( 37.14 % ) " "Info: Total cell delay = 4.595 ns ( 37.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.778 ns ( 62.86 % ) " "Info: Total interconnect delay = 7.778 ns ( 62.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhishi" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/zhishi.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "12.373 ns" { msec[1] Mux~966 Mux~967 Mux~968 daout[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "12.373 ns" { msec[1] msec[1]~out0 Mux~966 Mux~967 Mux~968 daout[1] } { 0.000ns 0.000ns 5.744ns 0.447ns 0.182ns 1.405ns } { 0.000ns 1.475ns 0.590ns 0.292ns 0.114ns 2.124ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 11 00:05:02 2008 " "Info: Processing ended: Wed Jun 11 00:05:02 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}