fenpin.tan.qmsg

VHDL语言设计的秒表

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register enter\[7\] register enter\[27\] 187.72 MHz 5.327 ns Internal " "Info: Clock \"clk\" has Internal fmax of 187.72 MHz between source register \"enter\[7\]\" and destination register \"enter\[27\]\" (period= 5.327 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.066 ns + Longest register register " "Info: + Longest register to register delay is 5.066 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns enter\[7\] 1 REG LC_X10_Y17_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y17_N3; Fanout = 4; REG Node = 'enter\[7\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { enter[7] } "NODE_NAME" } "" } } { "fenpin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/fenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.268 ns) + CELL(0.564 ns) 1.832 ns add~608 2 COMB LC_X11_Y16_N1 2 " "Info: 2: + IC(1.268 ns) + CELL(0.564 ns) = 1.832 ns; Loc. = LC_X11_Y16_N1; Fanout = 2; COMB Node = 'add~608'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.832 ns" { enter[7] add~608 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.910 ns add~588 3 COMB LC_X11_Y16_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.910 ns; Loc. = LC_X11_Y16_N2; Fanout = 2; COMB Node = 'add~588'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.078 ns" { add~608 add~588 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.988 ns add~583 4 COMB LC_X11_Y16_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.988 ns; Loc. = LC_X11_Y16_N3; Fanout = 2; COMB Node = 'add~583'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.078 ns" { add~588 add~583 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 2.166 ns add~578 5 COMB LC_X11_Y16_N4 6 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 2.166 ns; Loc. = LC_X11_Y16_N4; Fanout = 6; COMB Node = 'add~578'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.178 ns" { add~583 add~578 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 2.374 ns add~563 6 COMB LC_X11_Y16_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.208 ns) = 2.374 ns; Loc. = LC_X11_Y16_N9; Fanout = 6; COMB Node = 'add~563'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.208 ns" { add~578 add~563 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.510 ns add~538 7 COMB LC_X11_Y15_N4 6 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 2.510 ns; Loc. = LC_X11_Y15_N4; Fanout = 6; COMB Node = 'add~538'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.136 ns" { add~563 add~538 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 2.718 ns add~513 8 COMB LC_X11_Y15_N9 6 " "Info: 8: + IC(0.000 ns) + CELL(0.208 ns) = 2.718 ns; Loc. = LC_X11_Y15_N9; Fanout = 6; COMB Node = 'add~513'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.208 ns" { add~538 add~513 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 3.397 ns add~501 9 COMB LC_X11_Y14_N1 1 " "Info: 9: + IC(0.000 ns) + CELL(0.679 ns) = 3.397 ns; Loc. = LC_X11_Y14_N1; Fanout = 1; COMB Node = 'add~501'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.679 ns" { add~513 add~501 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.554 ns) + CELL(0.115 ns) 5.066 ns enter\[27\] 10 REG LC_X10_Y17_N1 4 " "Info: 10: + IC(1.554 ns) + CELL(0.115 ns) = 5.066 ns; Loc. = LC_X10_Y17_N1; Fanout = 4; REG Node = 'enter\[27\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.669 ns" { add~501 enter[27] } "NODE_NAME" } "" } } { "fenpin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/fenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.244 ns ( 44.30 % ) " "Info: Total cell delay = 2.244 ns ( 44.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.822 ns ( 55.70 % ) " "Info: Total interconnect delay = 2.822 ns ( 55.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "5.066 ns" { enter[7] add~608 add~588 add~583 add~578 add~563 add~538 add~513 add~501 enter[27] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "5.066 ns" { enter[7] add~608 add~588 add~583 add~578 add~563 add~538 add~513 add~501 enter[27] } { 0.000ns 1.268ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.554ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.208ns 0.136ns 0.208ns 0.679ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.245 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "fenpin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/fenpin.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns enter\[27\] 2 REG LC_X10_Y17_N1 4 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X10_Y17_N1; Fanout = 4; REG Node = 'enter\[27\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.776 ns" { clk enter[27] } "NODE_NAME" } "" } } { "fenpin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/fenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.245 ns" { clk enter[27] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 enter[27] } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.245 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "fenpin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/fenpin.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns enter\[7\] 2 REG LC_X10_Y17_N3 4 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X10_Y17_N3; Fanout = 4; REG Node = 'enter\[7\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.776 ns" { clk enter[7] } "NODE_NAME" } "" } } { "fenpin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/fenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.245 ns" { clk enter[7] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 enter[7] } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.245 ns" { clk enter[27] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 enter[27] } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.245 ns" { clk enter[7] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 enter[7] } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "fenpin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/fenpin.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "fenpin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/fenpin.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "5.066 ns" { enter[7] add~608 add~588 add~583 add~578 add~563 add~538 add~513 add~501 enter[27] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "5.066 ns" { enter[7] add~608 add~588 add~583 add~578 add~563 add~538 add~513 add~501 enter[27] } { 0.000ns 1.268ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.554ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.208ns 0.136ns 0.208ns 0.679ns 0.115ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.245 ns" { clk enter[27] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 enter[27] } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.245 ns" { clk enter[7] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { clk clk~out0 enter[7] } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk newclk enter\[20\] 11.999 ns register " "Info: tco from clock \"clk\" to destination pin \"newclk\" through register \"enter\[20\]\" is 11.999 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.210 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.210 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "fenpin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/fenpin.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.711 ns) 3.210 ns enter\[20\] 2 REG LC_X9_Y15_N8 3 " "Info: 2: + IC(1.030 ns) + CELL(0.711 ns) = 3.210 ns; Loc. = LC_X9_Y15_N8; Fanout = 3; REG Node = 'enter\[20\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.741 ns" { clk enter[20] } "NODE_NAME" } "" } } { "fenpin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/fenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.91 % ) " "Info: Total cell delay = 2.180 ns ( 67.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.030 ns ( 32.09 % ) " "Info: Total interconnect delay = 1.030 ns ( 32.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.210 ns" { clk enter[20] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.210 ns" { clk clk~out0 enter[20] } { 0.000ns 0.000ns 1.030ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "fenpin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/fenpin.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.565 ns + Longest register pin " "Info: + Longest register to pin delay is 8.565 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns enter\[20\] 1 REG LC_X9_Y15_N8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y15_N8; Fanout = 3; REG Node = 'enter\[20\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { enter[20] } "NODE_NAME" } "" } } { "fenpin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/fenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.162 ns) + CELL(0.590 ns) 1.752 ns rtl~289 2 COMB LC_X9_Y15_N6 1 " "Info: 2: + IC(1.162 ns) + CELL(0.590 ns) = 1.752 ns; Loc. = LC_X9_Y15_N6; Fanout = 1; COMB Node = 'rtl~289'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.752 ns" { enter[20] rtl~289 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.237 ns) + CELL(0.292 ns) 3.281 ns rtl~291 3 COMB LC_X10_Y17_N8 1 " "Info: 3: + IC(1.237 ns) + CELL(0.292 ns) = 3.281 ns; Loc. = LC_X10_Y17_N8; Fanout = 1; COMB Node = 'rtl~291'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.529 ns" { rtl~289 rtl~291 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.448 ns) + CELL(0.292 ns) 4.021 ns rtl~0 4 COMB LC_X10_Y17_N7 4 " "Info: 4: + IC(0.448 ns) + CELL(0.292 ns) = 4.021 ns; Loc. = LC_X10_Y17_N7; Fanout = 4; COMB Node = 'rtl~0'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.740 ns" { rtl~291 rtl~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.420 ns) + CELL(2.124 ns) 8.565 ns newclk 5 PIN PIN_23 0 " "Info: 5: + IC(2.420 ns) + CELL(2.124 ns) = 8.565 ns; Loc. = PIN_23; Fanout = 0; PIN Node = 'newclk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "4.544 ns" { rtl~0 newclk } "NODE_NAME" } "" } } { "fenpin.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/fenpin.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.298 ns ( 38.51 % ) " "Info: Total cell delay = 3.298 ns ( 38.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.267 ns ( 61.49 % ) " "Info: Total interconnect delay = 5.267 ns ( 61.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.565 ns" { enter[20] rtl~289 rtl~291 rtl~0 newclk } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.565 ns" { enter[20] rtl~289 rtl~291 rtl~0 newclk } { 0.000ns 1.162ns 1.237ns 0.448ns 2.420ns } { 0.000ns 0.590ns 0.292ns 0.292ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.210 ns" { clk enter[20] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.210 ns" { clk clk~out0 enter[20] } { 0.000ns 0.000ns 1.030ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenpin" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/fenpin.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.565 ns" { enter[20] rtl~289 rtl~291 rtl~0 newclk } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.565 ns" { enter[20] rtl~289 rtl~291 rtl~0 newclk } { 0.000ns 1.162ns 1.237ns 0.448ns 2.420ns } { 0.000ns 0.590ns 0.292ns 0.292ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 11 00:43:27 2008 " "Info: Processing ended: Wed Jun 11 00:43:27 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}