miba.sim.qmsg

来自「VHDL语言设计的秒表」· QMSG 代码 · 共 6 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jun 21 18:36:08 2008 " "Info: Processing started: Sat Jun 21 18:36:08 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off miba -c miba " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off miba -c miba" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Error" "ESIM_DAT_NOT_RAN" "" "Error: Can't continue simulation because delay annotation information for design is missing" {  } {  } 0 0 "Can't continue simulation because delay annotation information for design is missing" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Simulator 1  0 s Quartus II " "Error: Quartus II Simulator was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Sat Jun 21 18:36:09 2008 " "Error: Processing ended: Sat Jun 21 18:36:09 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}