fenpin.vhd

来自「VHDL语言设计的秒表」· VHDL 代码 · 共 28 行

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY fenpin IS
	PORT(
		clk  : IN	STD_LOGIC;
        newclk : OUT	STD_LOGIC);
		
END entity  fenpin ;
ARCHITECTURE fun OF  fenpin IS
signal enter: integer;
begin
process(clk)is
begin
if clk'event and clk='1' then
if enter=40 then enter<=0;
else enter<=enter+1;
end if;
end if;
end process;

process(enter)is
begin
if enter=40 then newclk<='1';
else newclk<='0';
end if;
end process;
end fun;