deled.vhd

来自「VHDL语言设计的秒表」· VHDL 代码 · 共 27 行

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY deled IS
	PORT(num: IN	std_logic_vector( 3 downto 0);
		 led: OUT   std_logic_vector(6 downto 0));
END deled;
ARCHITECTURE fun OF deled IS
BEGIN
	  led <= "0111111" when num= "0000" else
	   		 "0000110" when num= "0001" else
	   		 "1011011" when num= "0010" else
	    	 "1001111" when num= "0011" else
	    	 "1100110" when num= "0100" else
	    	 "1101101" when num= "0101" else
	    	 "1111101" when num= "0110" else
	    	 "0000111" when num= "0111" else
	    	 "1111111" when num= "1000" else
	    	 "1101111" when num= "1001" else
	    	 "1110111" when num= "1010" else
	    	 "1111100" when num= "1011" else
	    	 "0111001" when num= "1100" else
	    	 "1100011" when num= "1101" else
	    	 "1111001" when num= "1110" else
	    	 "1110001" when num= "1111" ;
	END fun;