zhishi.tan.rpt

来自「VHDL语言设计的秒表」· RPT 代码 · 共 213 行 · 第 1/2 页

; N/A   ; None         ; 10.048 ns  ; count[1] ; daout[1] ; clk1       ;
; N/A   ; None         ; 9.947 ns   ; count[1] ; daout[2] ; clk1       ;
; N/A   ; None         ; 9.772 ns   ; count[0] ; daout[2] ; clk1       ;
; N/A   ; None         ; 9.694 ns   ; count[0] ; daout[0] ; clk1       ;
; N/A   ; None         ; 9.387 ns   ; count[1] ; daout[0] ; clk1       ;
; N/A   ; None         ; 9.038 ns   ; count[2] ; daout[1] ; clk1       ;
; N/A   ; None         ; 8.962 ns   ; count[0] ; daout[3] ; clk1       ;
; N/A   ; None         ; 8.862 ns   ; count[2] ; daout[2] ; clk1       ;
; N/A   ; None         ; 8.768 ns   ; count[2] ; daout[3] ; clk1       ;
; N/A   ; None         ; 8.163 ns   ; count[2] ; daout[0] ; clk1       ;
; N/A   ; None         ; 7.594 ns   ; count[1] ; daout[3] ; clk1       ;
; N/A   ; None         ; 7.205 ns   ; count[2] ; sel[2]   ; clk1       ;
; N/A   ; None         ; 7.202 ns   ; count[1] ; sel[1]   ; clk1       ;
; N/A   ; None         ; 7.202 ns   ; count[0] ; sel[0]   ; clk1       ;
+-------+--------------+------------+----------+----------+------------+


+--------------------------------------------------------------------+
; tpd                                                                ;
+-------+-------------------+-----------------+-----------+----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From      ; To       ;
+-------+-------------------+-----------------+-----------+----------+
; N/A   ; None              ; 12.373 ns       ; msec[1]   ; daout[1] ;
; N/A   ; None              ; 11.989 ns       ; msec[4]   ; daout[0] ;
; N/A   ; None              ; 11.680 ns       ; msec[0]   ; daout[0] ;
; N/A   ; None              ; 11.558 ns       ; sec[4]    ; daout[0] ;
; N/A   ; None              ; 11.402 ns       ; minute[5] ; daout[1] ;
; N/A   ; None              ; 11.397 ns       ; sec[0]    ; daout[0] ;
; N/A   ; None              ; 11.335 ns       ; minute[2] ; daout[2] ;
; N/A   ; None              ; 11.237 ns       ; msec[2]   ; daout[2] ;
; N/A   ; None              ; 11.234 ns       ; sec[5]    ; daout[1] ;
; N/A   ; None              ; 11.210 ns       ; minute[0] ; daout[0] ;
; N/A   ; None              ; 11.178 ns       ; sec[1]    ; daout[1] ;
; N/A   ; None              ; 11.134 ns       ; minute[3] ; daout[3] ;
; N/A   ; None              ; 11.121 ns       ; minute[1] ; daout[1] ;
; N/A   ; None              ; 11.111 ns       ; minute[6] ; daout[2] ;
; N/A   ; None              ; 10.918 ns       ; sec[3]    ; daout[3] ;
; N/A   ; None              ; 10.878 ns       ; sec[6]    ; daout[2] ;
; N/A   ; None              ; 10.846 ns       ; msec[6]   ; daout[2] ;
; N/A   ; None              ; 10.512 ns       ; sec[2]    ; daout[2] ;
; N/A   ; None              ; 10.427 ns       ; msec[5]   ; daout[1] ;
; N/A   ; None              ; 10.389 ns       ; minute[4] ; daout[0] ;
; N/A   ; None              ; 10.334 ns       ; msec[3]   ; daout[3] ;
; N/A   ; None              ; 10.000 ns       ; msec[7]   ; daout[3] ;
+-------+-------------------+-----------------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Wed Jun 11 00:05:02 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off zhishi -c zhishi --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk1" is an undefined clock
Info: Clock "clk1" Internal fmax is restricted to 275.03 MHz between source register "count[2]" and destination register "count[0]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.201 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y23_N0; Fanout = 10; REG Node = 'count[2]'
            Info: 2: + IC(0.594 ns) + CELL(0.607 ns) = 1.201 ns; Loc. = LC_X1_Y23_N6; Fanout = 13; REG Node = 'count[0]'
            Info: Total cell delay = 0.607 ns ( 50.54 % )
            Info: Total interconnect delay = 0.594 ns ( 49.46 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk1" to destination register is 3.245 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 3; CLK Node = 'clk1'
                Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X1_Y23_N6; Fanout = 13; REG Node = 'count[0]'
                Info: Total cell delay = 2.180 ns ( 67.18 % )
                Info: Total interconnect delay = 1.065 ns ( 32.82 % )
            Info: - Longest clock path from clock "clk1" to source register is 3.245 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 3; CLK Node = 'clk1'
                Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X1_Y23_N0; Fanout = 10; REG Node = 'count[2]'
                Info: Total cell delay = 2.180 ns ( 67.18 % )
                Info: Total interconnect delay = 1.065 ns ( 32.82 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk1" to destination pin "daout[1]" through register "count[0]" is 10.151 ns
    Info: + Longest clock path from clock "clk1" to source register is 3.245 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 3; CLK Node = 'clk1'
        Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X1_Y23_N6; Fanout = 13; REG Node = 'count[0]'
        Info: Total cell delay = 2.180 ns ( 67.18 % )
        Info: Total interconnect delay = 1.065 ns ( 32.82 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 6.682 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y23_N6; Fanout = 13; REG Node = 'count[0]'
        Info: 2: + IC(1.676 ns) + CELL(0.442 ns) = 2.118 ns; Loc. = LC_X4_Y26_N8; Fanout = 1; COMB Node = 'Mux~966'
        Info: 3: + IC(0.447 ns) + CELL(0.292 ns) = 2.857 ns; Loc. = LC_X4_Y26_N6; Fanout = 1; COMB Node = 'Mux~967'
        Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 3.153 ns; Loc. = LC_X4_Y26_N7; Fanout = 1; COMB Node = 'Mux~968'
        Info: 5: + IC(1.405 ns) + CELL(2.124 ns) = 6.682 ns; Loc. = PIN_1; Fanout = 0; PIN Node = 'daout[1]'
        Info: Total cell delay = 2.972 ns ( 44.48 % )
        Info: Total interconnect delay = 3.710 ns ( 55.52 % )
Info: Longest tpd from source pin "msec[1]" to destination pin "daout[1]" is 12.373 ns
    Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_225; Fanout = 1; PIN Node = 'msec[1]'
    Info: 2: + IC(5.744 ns) + CELL(0.590 ns) = 7.809 ns; Loc. = LC_X4_Y26_N8; Fanout = 1; COMB Node = 'Mux~966'
    Info: 3: + IC(0.447 ns) + CELL(0.292 ns) = 8.548 ns; Loc. = LC_X4_Y26_N6; Fanout = 1; COMB Node = 'Mux~967'
    Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 8.844 ns; Loc. = LC_X4_Y26_N7; Fanout = 1; COMB Node = 'Mux~968'
    Info: 5: + IC(1.405 ns) + CELL(2.124 ns) = 12.373 ns; Loc. = PIN_1; Fanout = 0; PIN Node = 'daout[1]'
    Info: Total cell delay = 4.595 ns ( 37.14 % )
    Info: Total interconnect delay = 7.778 ns ( 62.86 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jun 11 00:05:02 2008
    Info: Elapsed time: 00:00:02