second.vhd

VHDL语言设计的秒表

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY second IS
	PORT(
		clk, reset,setsec  : IN	STD_LOGIC;
		enmin  : OUT	STD_LOGIC;
		daout: out std_logic_vector (6 downto 0));
END entity  second ;
ARCHITECTURE fun OF  second IS
	SIGNAL count: STD_LOGIC_VECTOR( 6 downto 0);
BEGIN
    daout <= count;
  process ( clk,reset,setsec ) 
   begin 
     if (reset='0') then
          count <= "0000000";
     elsif (setsec ='0') then                            --
     elsif (clk' event and clk='1') then
       
           if (count(3 downto 0)="1001") then
               if (count <16#60#) then
               		if (count="1011001") then
           				enmin <='1'; 
           				count<="0000000";           				          		
           	   		ELSE
           	   		   count<=count+7; 
           	   		end if;
           	   	else 
                   count<="0000000";
               end if;
            elsif(count <16#60#) then 
               count <= count + 1;
               enmin <='0' after 100 ns;--?
            else
            	count<="0000000";
            end if;
      end if;
    
   end process;
END fun;