msecond.tan.rpt

VHDL语言设计的秒表

; N/A   ; None         ; 11.782 ns  ; count[3]   ; daout[3] ; clk        ;
+-------+--------------+------------+------------+----------+------------+


+---------------------------------------------------------------------------+
; th                                                                        ;
+---------------+-------------+-----------+---------+------------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To         ; To Clock ;
+---------------+-------------+-----------+---------+------------+----------+
; N/A           ; None        ; 0.848 ns  ; setmsec ; count[0]   ; clk      ;
; N/A           ; None        ; 0.848 ns  ; setmsec ; count[1]   ; clk      ;
; N/A           ; None        ; 0.848 ns  ; setmsec ; count[3]   ; clk      ;
; N/A           ; None        ; 0.848 ns  ; setmsec ; count[2]   ; clk      ;
; N/A           ; None        ; 0.848 ns  ; setmsec ; count[7]   ; clk      ;
; N/A           ; None        ; 0.848 ns  ; setmsec ; count[4]   ; clk      ;
; N/A           ; None        ; 0.848 ns  ; setmsec ; count[5]   ; clk      ;
; N/A           ; None        ; 0.848 ns  ; setmsec ; count[6]   ; clk      ;
; N/A           ; None        ; 0.000 ns  ; setmsec ; ensec~reg0 ; clk      ;
; N/A           ; None        ; -0.171 ns ; reset   ; ensec~reg0 ; clk      ;
+---------------+-------------+-----------+---------+------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Wed Jun 11 15:20:11 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off msecond -c msecond --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 255.56 MHz between source register "count[1]" and destination register "count[6]" (period= 3.913 ns)
    Info: + Longest register to register delay is 3.652 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y23_N1; Fanout = 5; REG Node = 'count[1]'
        Info: 2: + IC(0.531 ns) + CELL(0.590 ns) = 1.121 ns; Loc. = LC_X1_Y23_N9; Fanout = 8; COMB Node = 'rtl~43'
        Info: 3: + IC(1.013 ns) + CELL(0.423 ns) = 2.557 ns; Loc. = LC_X1_Y23_N2; Fanout = 2; COMB Node = 'count[2]~343'
        Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 2.635 ns; Loc. = LC_X1_Y23_N3; Fanout = 2; COMB Node = 'count[3]~347'
        Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 2.813 ns; Loc. = LC_X1_Y23_N4; Fanout = 3; COMB Node = 'count[4]~351'
        Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 3.652 ns; Loc. = LC_X1_Y23_N6; Fanout = 6; REG Node = 'count[6]'
        Info: Total cell delay = 2.108 ns ( 57.72 % )
        Info: Total interconnect delay = 1.544 ns ( 42.28 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 8.290 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 9; CLK Node = 'clk'
            Info: 2: + IC(6.110 ns) + CELL(0.711 ns) = 8.290 ns; Loc. = LC_X1_Y23_N6; Fanout = 6; REG Node = 'count[6]'
            Info: Total cell delay = 2.180 ns ( 26.30 % )
            Info: Total interconnect delay = 6.110 ns ( 73.70 % )
        Info: - Longest clock path from clock "clk" to source register is 8.290 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 9; CLK Node = 'clk'
            Info: 2: + IC(6.110 ns) + CELL(0.711 ns) = 8.290 ns; Loc. = LC_X1_Y23_N1; Fanout = 5; REG Node = 'count[1]'
            Info: Total cell delay = 2.180 ns ( 26.30 % )
            Info: Total interconnect delay = 6.110 ns ( 73.70 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "ensec~reg0" (data pin = "reset", clock pin = "clk") is 0.223 ns
    Info: + Longest pin to register delay is 8.476 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_3; Fanout = 9; PIN Node = 'reset'
        Info: 2: + IC(5.410 ns) + CELL(0.590 ns) = 7.469 ns; Loc. = LC_X2_Y23_N5; Fanout = 1; COMB Node = 'ensec~263'
        Info: 3: + IC(0.400 ns) + CELL(0.607 ns) = 8.476 ns; Loc. = LC_X2_Y23_N4; Fanout = 2; REG Node = 'ensec~reg0'
        Info: Total cell delay = 2.666 ns ( 31.45 % )
        Info: Total interconnect delay = 5.810 ns ( 68.55 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 8.290 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(6.110 ns) + CELL(0.711 ns) = 8.290 ns; Loc. = LC_X2_Y23_N4; Fanout = 2; REG Node = 'ensec~reg0'
        Info: Total cell delay = 2.180 ns ( 26.30 % )
        Info: Total interconnect delay = 6.110 ns ( 73.70 % )
Info: tco from clock "clk" to destination pin "ensec" through register "ensec~reg0" is 12.498 ns
    Info: + Longest clock path from clock "clk" to source register is 8.290 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(6.110 ns) + CELL(0.711 ns) = 8.290 ns; Loc. = LC_X2_Y23_N4; Fanout = 2; REG Node = 'ensec~reg0'
        Info: Total cell delay = 2.180 ns ( 26.30 % )
        Info: Total interconnect delay = 6.110 ns ( 73.70 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.984 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y23_N4; Fanout = 2; REG Node = 'ensec~reg0'
        Info: 2: + IC(1.860 ns) + CELL(2.124 ns) = 3.984 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'ensec'
        Info: Total cell delay = 2.124 ns ( 53.31 % )
        Info: Total interconnect delay = 1.860 ns ( 46.69 % )
Info: th for register "count[0]" (data pin = "setmsec", clock pin = "clk") is 0.848 ns
    Info: + Longest clock path from clock "clk" to destination register is 8.290 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(6.110 ns) + CELL(0.711 ns) = 8.290 ns; Loc. = LC_X1_Y23_N0; Fanout = 5; REG Node = 'count[0]'
        Info: Total cell delay = 2.180 ns ( 26.30 % )
        Info: Total interconnect delay = 6.110 ns ( 73.70 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.457 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_4; Fanout = 9; PIN Node = 'setmsec'
        Info: 2: + IC(5.121 ns) + CELL(0.867 ns) = 7.457 ns; Loc. = LC_X1_Y23_N0; Fanout = 5; REG Node = 'count[0]'
        Info: Total cell delay = 2.336 ns ( 31.33 % )
        Info: Total interconnect delay = 5.121 ns ( 68.67 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jun 11 15:20:13 2008
    Info: Elapsed time: 00:00:04