miaobiao.tan.summary

VHDL语言设计的秒表

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 1.389 ns
From           : set
To             : msecond:inst1|count[5]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 38.105 ns
From           : minute:inst3|count[0]
To             : led[4]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 4.716 ns
From           : reset
To             : second:inst2|enmin
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 225.73 MHz ( period = 4.430 ns )
From           : msecond:inst1|count[1]
To             : msecond:inst1|count[3]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clkdsp'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : zhishi:inst|count[0]
To             : zhishi:inst|count[2]
From Clock     : clkdsp
To Clock       : clkdsp
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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