秒表2.txt

VHDL语言设计的秒表

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity watch is
port(sel:out std_logic_vector(6 downto 1);--片选信号
     seg:out std_logic_vector(7 downto 0);--数码管输出信号
     beginstop:in std.logic;--开始、停止计数
     reset:in std_logic;--复位
     cp2:in std_logic);
end watch;
architecture behave of watch is
signal num1:std_logic_vector(3 downto 0);
signal num2:std_logic_vector(3 downto 0);
signal num3:std_logic_vector(3 downto 0);
signal num4:std_logic_vector(3 downto 0);
signal num5:std_logic_vector(3 downto 0);
signal num6:std_logic_vector(3 downto 0);
signal num:std_logic_vector(3 downto 0);
signal numlet:std_logic_vector(2 downto 0);
signal count:std_logic_vector(17 downto 1);
signal selsig:std_logic_vector(6 downto 1);
signal segsig:std_logic_vector(7 downto 0);
signal cp1:std_logic;
signal cp3:std_logic;
  begin
    process(cp2)--分频
      begin
       if(cp2'event and cp2='1')then
         if(count="11000011010011111")then
           count<="00000000000000000";cp1<=not cp1;
         else count<=count+1;
         end if;
       end if;
         cp3<=count(10);
    end process;
    process(cp1)--计数控制。
      begin
        if reset='1' then num1(3 downto 0)<="0000";
                          num2(3 downto 0)<="0000";
                          num3(3 downto 0)<="0000";
                          num4(3 downto 0)<="0000";
                          num5(3 downto 0)<="0000";
                          num6(3 downto 0)<="0000";
         else if cp1'event and cp1='1' then
        if beginstop='1' then num1<=num1+1;
        if num1(3 downto 0)="1001" then
           num1(3 downto 0)<="0000";num2<=num2+1;
        if num2(3 downto 0)="1001" then
           num2(3 downto 0)<="0000";num3<=num3+1;
        if num3(3 downto 0)="1001" then
           num3(3 downto 0)<="0000";num4<=num4+1;
        if num4(3 downto 0)="1001" then
           num4(3 downto 0)<="0000";num5<=num5+1;
        if num5(3 downto 0)="1001" then
           num5(3 downto 0)<="0000";num6<=num6+1;
        if num6(3 downto 0)="1001" then
           num6(3 downto 0)<="0000";
        end if;end if;end if;end if;end if;end if;end if;
        end if;end if;
        end process;
    process(cp3)-- 显示控制
      begin
        if(cp3'event and cp3='1')then
          if(numlet(2 downto 0)="000")then
            num<=num1;selsig(6 downto 1)<="111110";end if;
          if(numlet(2 downto 0)="000")then
            num<=num2;selsig(6 downto 1)<="111101";end if;
          if(numlet(2 downto 0)="000")then
            num<=num3;selsig(6 downto 1)<="111011";end if;
          if(numlet(2 downto 0)="000")then
            num<=num4;selsig(6 downto 1)<="110111";end if;
          if(numlet(2 downto 0)="000")then
            num<=num5;selsig(6 downto 1)<="101111";end if;
            numlet(2 downto 0)<=numlet(2 downto 0)+1;
          if(numlet(2 downto 0)="101")then
            numlet(2 downto 0)<="000";num<=num6;
        selsig(6 downto 1)<="011111";end if;
        end if;
      if(num(3 downto 0)="0000") then
        segsig(7 downto 0)<="01111111";end if;  
      if(num(3 downto 0)="0001") then
        segsig(7 downto 0)<="00001101";end if;   
      if(num(3 downto 0)="0010") then
        segsig(7 downto 0)<="10110111";end if;  
      if(num(3 downto 0)="0011") then
        segsig(7 downto 0)<="10011111";end if;    
      if(num(3 downto 0)="0100") then
        segsig(7 downto 0)<="11001101";end if;    
      if(num(3 downto 0)="0101") then
        segsig(7 downto 0)<="11011011";end if;    
      if(num(3 downto 0)="0110") then
        segsig(7 downto 0)<="11111011";end if;   
      if(num(3 downto 0)="0111") then
        segsig(7 downto 0)<="00001111";end if;  
      if(num(3 downto 0)="1000") then
        segsig(7 downto 0)<="11111111";end if;   
      if(num(3 downto 0)="1001") then
        segsig(7 downto 0)<="11011111";end if;    
     end process;
        sel<=selsig;
     seg(7 downto 0)<=segsig(7 downto 0);
end behave;