alert.vhd

VHDL语言设计的秒表

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY alert IS
	PORT(
		clk  : IN	STD_LOGIC;
		dain : IN	STD_LOGIC_VECTOR(6 DOWNTO 0);
		lamp : OUT  STD_LOGIC_VECTOR(2 DOWNTO 0));
END alert ;
ARCHITECTURE fun OF alert IS
	signal count : std_logic_vector( 1 downto 0);
BEGIN
lamper:process(clk)
		begin
			if (rising_edge(clk))then 
				if (count <= "10") then
					if (count ="00") then
						lamp <= "001" ;
					elsif (count = "01") then
						lamp <= "010" ;
					elsif(count="10") then 
						lamp <= "100" ;
					end if;
					count <= count + 1;
				else 
				count <= "00";
				end if;		
		 	end if;		 		
	end process lamper;
END fun ;