📄 alert.tan.rpt
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Timing Analyzer report for alert
Fri Jun 06 22:11:49 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+--------------+--------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+--------------+--------------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 7.173 ns ; lamp[0]~reg0 ; lamp[0] ; clk ; -- ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; lamp[1]~reg0 ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+--------------+--------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C12Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; lamp[2]~reg0 ; clk ; clk ; None ; None ; 2.518 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; lamp[1]~reg0 ; clk ; clk ; None ; None ; 2.518 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1] ; lamp[2]~reg0 ; clk ; clk ; None ; None ; 2.233 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1] ; lamp[1]~reg0 ; clk ; clk ; None ; None ; 2.233 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; count[1] ; clk ; clk ; None ; None ; 1.321 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; lamp[0]~reg0 ; clk ; clk ; None ; None ; 1.320 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lamp[0]~reg0 ; lamp[0]~reg0 ; clk ; clk ; None ; None ; 1.105 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1] ; lamp[0]~reg0 ; clk ; clk ; None ; None ; 1.069 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1] ; count[1] ; clk ; clk ; None ; None ; 1.066 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; count[0] ; clk ; clk ; None ; None ; 0.880 ns ;
+-------+------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A ; None ; 7.173 ns ; lamp[0]~reg0 ; lamp[0] ; clk ;
; N/A ; None ; 6.738 ns ; lamp[1]~reg0 ; lamp[1] ; clk ;
; N/A ; None ; 6.737 ns ; lamp[2]~reg0 ; lamp[2] ; clk ;
+-------+--------------+------------+--------------+---------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Fri Jun 06 22:11:48 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off alert -c alert --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "count[0]" and destination register "lamp[2]~reg0"
Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 2.518 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y26_N6; Fanout = 5; REG Node = 'count[0]'
Info: 2: + IC(0.580 ns) + CELL(0.590 ns) = 1.170 ns; Loc. = LC_X1_Y26_N9; Fanout = 2; COMB Node = 'lamp[0]~133'
Info: 3: + IC(0.481 ns) + CELL(0.867 ns) = 2.518 ns; Loc. = LC_X1_Y26_N8; Fanout = 1; REG Node = 'lamp[2]~reg0'
Info: Total cell delay = 1.457 ns ( 57.86 % )
Info: Total interconnect delay = 1.061 ns ( 42.14 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 3.245 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'
Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X1_Y26_N8; Fanout = 1; REG Node = 'lamp[2]~reg0'
Info: Total cell delay = 2.180 ns ( 67.18 % )
Info: Total interconnect delay = 1.065 ns ( 32.82 % )
Info: - Longest clock path from clock "clk" to source register is 3.245 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'
Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X1_Y26_N6; Fanout = 5; REG Node = 'count[0]'
Info: Total cell delay = 2.180 ns ( 67.18 % )
Info: Total interconnect delay = 1.065 ns ( 32.82 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "lamp[0]" through register "lamp[0]~reg0" is 7.173 ns
Info: + Longest clock path from clock "clk" to source register is 3.245 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'
Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X1_Y26_N4; Fanout = 2; REG Node = 'lamp[0]~reg0'
Info: Total cell delay = 2.180 ns ( 67.18 % )
Info: Total interconnect delay = 1.065 ns ( 32.82 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 3.704 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y26_N4; Fanout = 2; REG Node = 'lamp[0]~reg0'
Info: 2: + IC(1.580 ns) + CELL(2.124 ns) = 3.704 ns; Loc. = PIN_3; Fanout = 0; PIN Node = 'lamp[0]'
Info: Total cell delay = 2.124 ns ( 57.34 % )
Info: Total interconnect delay = 1.580 ns ( 42.66 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Fri Jun 06 22:11:49 2008
Info: Elapsed time: 00:00:02
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