alert.fit.eqn

VHDL语言设计的秒表

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--A1L16Q is lamp[0]~reg0 at LC_X1_Y26_N4
--operation mode is normal

A1L16Q_lut_out = count[0] & A1L16Q & count[1] # !count[0] & (!count[1]);
A1L16Q = DFFEAS(A1L16Q_lut_out, GLOBAL(clk), VCC, , , , , , );


--A1L18Q is lamp[1]~reg0 at LC_X1_Y26_N5
--operation mode is normal

A1L18Q_lut_out = count[0] & (!count[1]);
A1L18Q = DFFEAS(A1L18Q_lut_out, GLOBAL(clk), VCC, , A1L15, , , , );


--A1L20Q is lamp[2]~reg0 at LC_X1_Y26_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L20Q_lut_out = GND;
A1L20Q = DFFEAS(A1L20Q_lut_out, GLOBAL(clk), VCC, , A1L15, count[1], , , VCC);


--count[0] is count[0] at LC_X1_Y26_N6
--operation mode is normal

count[0]_lut_out = !count[0];
count[0] = DFFEAS(count[0]_lut_out, GLOBAL(clk), VCC, , , , , , );


--count[1] is count[1] at LC_X1_Y26_N2
--operation mode is normal

count[1]_lut_out = count[0] $ (count[1]);
count[1] = DFFEAS(count[1]_lut_out, GLOBAL(clk), VCC, , , , , , );


--A1L15 is lamp[0]~133 at LC_X1_Y26_N9
--operation mode is normal

A1L15 = !count[1] # !count[0];


--dain[0] is dain[0] at PIN_87
--operation mode is input

dain[0] = INPUT();


--dain[1] is dain[1] at PIN_170
--operation mode is input

dain[1] = INPUT();


--dain[2] is dain[2] at PIN_7
--operation mode is input

dain[2] = INPUT();


--dain[3] is dain[3] at PIN_82
--operation mode is input

dain[3] = INPUT();


--dain[4] is dain[4] at PIN_54
--operation mode is input

dain[4] = INPUT();


--dain[5] is dain[5] at PIN_119
--operation mode is input

dain[5] = INPUT();


--dain[6] is dain[6] at PIN_166
--operation mode is input

dain[6] = INPUT();


--clk is clk at PIN_29
--operation mode is input

clk = INPUT();


--lamp[0] is lamp[0] at PIN_3
--operation mode is output

lamp[0] = OUTPUT(A1L16Q);


--lamp[1] is lamp[1] at PIN_1
--operation mode is output

lamp[1] = OUTPUT(A1L18Q);


--lamp[2] is lamp[2] at PIN_2
--operation mode is output

lamp[2] = OUTPUT(A1L20Q);