msecond.vhd

VHDL语言设计的秒表

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY msecond IS
	PORT(
		clk, reset,setmsec : IN	STD_LOGIC;
		ensec  :  OUT	STD_LOGIC;
		daout: OUT  std_logic_vector (7 downto 0));
END entity msecond ;
ARCHITECTURE fun OF msecond  IS
	SIGNAL count: STD_LOGIC_VECTOR( 7 downto 0);
BEGIN
    daout <= count;
  process ( clk , reset , setmsec ) 
   begin 
   
	 if (reset='0') then
          count <= "00000000";
     elsif(setmsec ='0') then                    --
     elsif (clk 'event and clk='1') then
         
           if (count(3 downto 0)="1001") then
               if (count <16#A0#) then
               		if (count="10011001") then
           				ensec <='1'; 
           				count<="00000000";           				          		
           	   		ELSE
           	   		   count<=count+7; 
           	   		end if;
               else 
                   count<="00000000";
               end if;
           elsif (count < 16#A0#) then --当成功之后，尝试改成10之1秒形式
               count <= count+1;
               ensec <='0' after 100 ns;               
            else 
                   count<="00000000";                  
           end if;           
     end if;
    
  end process;
END fun;