minute.tan.rpt

VHDL语言设计的秒表

; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[4] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 2.557 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[4] ; count[0] ; clk        ; clk      ; None                        ; None                      ; 2.557 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[6] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 2.432 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[6] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 2.432 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[6] ; count[6] ; clk        ; clk      ; None                        ; None                      ; 2.432 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[6] ; count[4] ; clk        ; clk      ; None                        ; None                      ; 2.432 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[6] ; count[5] ; clk        ; clk      ; None                        ; None                      ; 2.432 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[6] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 2.432 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[6] ; count[0] ; clk        ; clk      ; None                        ; None                      ; 2.432 ns                ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+------------------------------------------------------------------+
; tsu                                                              ;
+-------+--------------+------------+--------+----------+----------+
; Slack ; Required tsu ; Actual tsu ; From   ; To       ; To Clock ;
+-------+--------------+------------+--------+----------+----------+
; N/A   ; None         ; -0.800 ns  ; setmin ; count[0] ; clk      ;
; N/A   ; None         ; -0.800 ns  ; setmin ; count[1] ; clk      ;
; N/A   ; None         ; -0.800 ns  ; setmin ; count[5] ; clk      ;
; N/A   ; None         ; -0.800 ns  ; setmin ; count[4] ; clk      ;
; N/A   ; None         ; -0.800 ns  ; setmin ; count[6] ; clk      ;
; N/A   ; None         ; -0.800 ns  ; setmin ; count[2] ; clk      ;
; N/A   ; None         ; -0.800 ns  ; setmin ; count[3] ; clk      ;
+-------+--------------+------------+--------+----------+----------+


+----------------------------------------------------------------------+
; tco                                                                  ;
+-------+--------------+------------+----------+----------+------------+
; Slack ; Required tco ; Actual tco ; From     ; To       ; From Clock ;
+-------+--------------+------------+----------+----------+------------+
; N/A   ; None         ; 12.231 ns  ; count[2] ; daout[2] ; clk        ;
; N/A   ; None         ; 12.222 ns  ; count[0] ; daout[0] ; clk        ;
; N/A   ; None         ; 12.218 ns  ; count[1] ; daout[1] ; clk        ;
; N/A   ; None         ; 12.212 ns  ; count[3] ; daout[3] ; clk        ;
; N/A   ; None         ; 11.771 ns  ; count[4] ; daout[4] ; clk        ;
; N/A   ; None         ; 11.770 ns  ; count[6] ; daout[6] ; clk        ;
; N/A   ; None         ; 11.770 ns  ; count[5] ; daout[5] ; clk        ;
+-------+--------------+------------+----------+----------+------------+


+------------------------------------------------------------------------+
; th                                                                     ;
+---------------+-------------+-----------+--------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To       ; To Clock ;
+---------------+-------------+-----------+--------+----------+----------+
; N/A           ; None        ; 0.852 ns  ; setmin ; count[0] ; clk      ;
; N/A           ; None        ; 0.852 ns  ; setmin ; count[1] ; clk      ;
; N/A           ; None        ; 0.852 ns  ; setmin ; count[5] ; clk      ;
; N/A           ; None        ; 0.852 ns  ; setmin ; count[4] ; clk      ;
; N/A           ; None        ; 0.852 ns  ; setmin ; count[6] ; clk      ;
; N/A           ; None        ; 0.852 ns  ; setmin ; count[2] ; clk      ;
; N/A           ; None        ; 0.852 ns  ; setmin ; count[3] ; clk      ;
+---------------+-------------+-----------+--------+----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Wed Jun 11 15:27:27 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off minute -c minute --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "count[1]" and destination register "count[3]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 3.295 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y23_N2; Fanout = 5; REG Node = 'count[1]'
            Info: 2: + IC(0.546 ns) + CELL(0.590 ns) = 1.136 ns; Loc. = LC_X1_Y23_N0; Fanout = 7; COMB Node = 'rtl~33'
            Info: 3: + IC(0.467 ns) + CELL(0.114 ns) = 1.717 ns; Loc. = LC_X1_Y23_N8; Fanout = 7; COMB Node = 'count[0]~297'
            Info: 4: + IC(0.466 ns) + CELL(1.112 ns) = 3.295 ns; Loc. = LC_X1_Y23_N4; Fanout = 4; REG Node = 'count[3]'
            Info: Total cell delay = 1.816 ns ( 55.11 % )
            Info: Total interconnect delay = 1.479 ns ( 44.89 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 8.278 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 7; CLK Node = 'clk'
                Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y23_N4; Fanout = 4; REG Node = 'count[3]'
                Info: Total cell delay = 2.180 ns ( 26.33 % )
                Info: Total interconnect delay = 6.098 ns ( 73.67 % )
            Info: - Longest clock path from clock "clk" to source register is 8.278 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 7; CLK Node = 'clk'
                Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y23_N2; Fanout = 5; REG Node = 'count[1]'
                Info: Total cell delay = 2.180 ns ( 26.33 % )
                Info: Total interconnect delay = 6.098 ns ( 73.67 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "count[0]" (data pin = "setmin", clock pin = "clk") is -0.800 ns
    Info: + Longest pin to register delay is 7.441 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 7; PIN Node = 'setmin'
        Info: 2: + IC(5.105 ns) + CELL(0.867 ns) = 7.441 ns; Loc. = LC_X1_Y23_N1; Fanout = 5; REG Node = 'count[0]'
        Info: Total cell delay = 2.336 ns ( 31.39 % )
        Info: Total interconnect delay = 5.105 ns ( 68.61 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 8.278 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 7; CLK Node = 'clk'
        Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y23_N1; Fanout = 5; REG Node = 'count[0]'
        Info: Total cell delay = 2.180 ns ( 26.33 % )
        Info: Total interconnect delay = 6.098 ns ( 73.67 % )
Info: tco from clock "clk" to destination pin "daout[2]" through register "count[2]" is 12.231 ns
    Info: + Longest clock path from clock "clk" to source register is 8.278 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 7; CLK Node = 'clk'
        Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y23_N3; Fanout = 5; REG Node = 'count[2]'
        Info: Total cell delay = 2.180 ns ( 26.33 % )
        Info: Total interconnect delay = 6.098 ns ( 73.67 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.729 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y23_N3; Fanout = 5; REG Node = 'count[2]'
        Info: 2: + IC(1.605 ns) + CELL(2.124 ns) = 3.729 ns; Loc. = PIN_7; Fanout = 0; PIN Node = 'daout[2]'
        Info: Total cell delay = 2.124 ns ( 56.96 % )
        Info: Total interconnect delay = 1.605 ns ( 43.04 % )
Info: th for register "count[0]" (data pin = "setmin", clock pin = "clk") is 0.852 ns
    Info: + Longest clock path from clock "clk" to destination register is 8.278 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 7; CLK Node = 'clk'
        Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X1_Y23_N1; Fanout = 5; REG Node = 'count[0]'
        Info: Total cell delay = 2.180 ns ( 26.33 % )
        Info: Total interconnect delay = 6.098 ns ( 73.67 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.441 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 7; PIN Node = 'setmin'
        Info: 2: + IC(5.105 ns) + CELL(0.867 ns) = 7.441 ns; Loc. = LC_X1_Y23_N1; Fanout = 5; REG Node = 'count[0]'
        Info: Total cell delay = 2.336 ns ( 31.39 % )
        Info: Total interconnect delay = 5.105 ns ( 68.61 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jun 11 15:27:29 2008
    Info: Elapsed time: 00:00:03