alert.map.eqn

VHDL语言设计的秒表

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--A1L16Q is lamp[0]~reg0
--operation mode is normal

A1L16Q_lut_out = count[0] & A1L16Q & count[1] # !count[0] & (!count[1]);
A1L16Q = DFFEAS(A1L16Q_lut_out, clk, VCC, , , , , , );


--A1L18Q is lamp[1]~reg0
--operation mode is normal

A1L18Q_lut_out = count[0] & (!count[1]);
A1L18Q = DFFEAS(A1L18Q_lut_out, clk, VCC, , A1L15, , , , );


--A1L20Q is lamp[2]~reg0
--operation mode is normal

A1L20Q_lut_out = count[1];
A1L20Q = DFFEAS(A1L20Q_lut_out, clk, VCC, , A1L15, , , , );


--count[0] is count[0]
--operation mode is normal

count[0]_lut_out = !count[0];
count[0] = DFFEAS(count[0]_lut_out, clk, VCC, , , , , , );


--count[1] is count[1]
--operation mode is normal

count[1]_lut_out = count[0] $ count[1];
count[1] = DFFEAS(count[1]_lut_out, clk, VCC, , , , , , );


--A1L15 is lamp[0]~133
--operation mode is normal

A1L15 = !count[1] # !count[0];


--dain[0] is dain[0]
--operation mode is input

dain[0] = INPUT();


--dain[1] is dain[1]
--operation mode is input

dain[1] = INPUT();


--dain[2] is dain[2]
--operation mode is input

dain[2] = INPUT();


--dain[3] is dain[3]
--operation mode is input

dain[3] = INPUT();


--dain[4] is dain[4]
--operation mode is input

dain[4] = INPUT();


--dain[5] is dain[5]
--operation mode is input

dain[5] = INPUT();


--dain[6] is dain[6]
--operation mode is input

dain[6] = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--lamp[0] is lamp[0]
--operation mode is output

lamp[0] = OUTPUT(A1L16Q);


--lamp[1] is lamp[1]
--operation mode is output

lamp[1] = OUTPUT(A1L18Q);


--lamp[2] is lamp[2]
--operation mode is output

lamp[2] = OUTPUT(A1L20Q);