fenpin.tan.rpt

来自「VHDL语言设计的秒表」· RPT 代码 · 共 389 行 · 第 1/5 页

; N/A   ; None         ; 10.739 ns  ; enter[19] ; newclk ; clk        ;
; N/A   ; None         ; 10.735 ns  ; enter[12] ; newclk ; clk        ;
; N/A   ; None         ; 10.732 ns  ; enter[6]  ; newclk ; clk        ;
; N/A   ; None         ; 10.655 ns  ; enter[24] ; newclk ; clk        ;
; N/A   ; None         ; 10.625 ns  ; enter[23] ; newclk ; clk        ;
; N/A   ; None         ; 10.440 ns  ; enter[11] ; newclk ; clk        ;
; N/A   ; None         ; 10.425 ns  ; enter[0]  ; newclk ; clk        ;
; N/A   ; None         ; 10.359 ns  ; enter[3]  ; newclk ; clk        ;
; N/A   ; None         ; 10.255 ns  ; enter[26] ; newclk ; clk        ;
; N/A   ; None         ; 10.145 ns  ; enter[4]  ; newclk ; clk        ;
; N/A   ; None         ; 9.872 ns   ; enter[1]  ; newclk ; clk        ;
; N/A   ; None         ; 9.821 ns   ; enter[5]  ; newclk ; clk        ;
; N/A   ; None         ; 9.674 ns   ; enter[27] ; newclk ; clk        ;
; N/A   ; None         ; 9.607 ns   ; enter[2]  ; newclk ; clk        ;
; N/A   ; None         ; 9.415 ns   ; enter[13] ; newclk ; clk        ;
; N/A   ; None         ; 9.248 ns   ; enter[7]  ; newclk ; clk        ;
+-------+--------------+------------+-----------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Wed Jun 11 00:43:26 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fenpin -c fenpin --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 187.72 MHz between source register "enter[7]" and destination register "enter[27]" (period= 5.327 ns)
    Info: + Longest register to register delay is 5.066 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y17_N3; Fanout = 4; REG Node = 'enter[7]'
        Info: 2: + IC(1.268 ns) + CELL(0.564 ns) = 1.832 ns; Loc. = LC_X11_Y16_N1; Fanout = 2; COMB Node = 'add~608'
        Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.910 ns; Loc. = LC_X11_Y16_N2; Fanout = 2; COMB Node = 'add~588'
        Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.988 ns; Loc. = LC_X11_Y16_N3; Fanout = 2; COMB Node = 'add~583'
        Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 2.166 ns; Loc. = LC_X11_Y16_N4; Fanout = 6; COMB Node = 'add~578'
        Info: 6: + IC(0.000 ns) + CELL(0.208 ns) = 2.374 ns; Loc. = LC_X11_Y16_N9; Fanout = 6; COMB Node = 'add~563'
        Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 2.510 ns; Loc. = LC_X11_Y15_N4; Fanout = 6; COMB Node = 'add~538'
        Info: 8: + IC(0.000 ns) + CELL(0.208 ns) = 2.718 ns; Loc. = LC_X11_Y15_N9; Fanout = 6; COMB Node = 'add~513'
        Info: 9: + IC(0.000 ns) + CELL(0.679 ns) = 3.397 ns; Loc. = LC_X11_Y14_N1; Fanout = 1; COMB Node = 'add~501'
        Info: 10: + IC(1.554 ns) + CELL(0.115 ns) = 5.066 ns; Loc. = LC_X10_Y17_N1; Fanout = 4; REG Node = 'enter[27]'
        Info: Total cell delay = 2.244 ns ( 44.30 % )
        Info: Total interconnect delay = 2.822 ns ( 55.70 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.245 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'
            Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X10_Y17_N1; Fanout = 4; REG Node = 'enter[27]'
            Info: Total cell delay = 2.180 ns ( 67.18 % )
            Info: Total interconnect delay = 1.065 ns ( 32.82 % )
        Info: - Longest clock path from clock "clk" to source register is 3.245 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'
            Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X10_Y17_N3; Fanout = 4; REG Node = 'enter[7]'
            Info: Total cell delay = 2.180 ns ( 67.18 % )
            Info: Total interconnect delay = 1.065 ns ( 32.82 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "newclk" through register "enter[20]" is 11.999 ns
    Info: + Longest clock path from clock "clk" to source register is 3.210 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'
        Info: 2: + IC(1.030 ns) + CELL(0.711 ns) = 3.210 ns; Loc. = LC_X9_Y15_N8; Fanout = 3; REG Node = 'enter[20]'
        Info: Total cell delay = 2.180 ns ( 67.91 % )
        Info: Total interconnect delay = 1.030 ns ( 32.09 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 8.565 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y15_N8; Fanout = 3; REG Node = 'enter[20]'
        Info: 2: + IC(1.162 ns) + CELL(0.590 ns) = 1.752 ns; Loc. = LC_X9_Y15_N6; Fanout = 1; COMB Node = 'rtl~289'
        Info: 3: + IC(1.237 ns) + CELL(0.292 ns) = 3.281 ns; Loc. = LC_X10_Y17_N8; Fanout = 1; COMB Node = 'rtl~291'
        Info: 4: + IC(0.448 ns) + CELL(0.292 ns) = 4.021 ns; Loc. = LC_X10_Y17_N7; Fanout = 4; COMB Node = 'rtl~0'
        Info: 5: + IC(2.420 ns) + CELL(2.124 ns) = 8.565 ns; Loc. = PIN_23; Fanout = 0; PIN Node = 'newclk'
        Info: Total cell delay = 3.298 ns ( 38.51 % )
        Info: Total interconnect delay = 5.267 ns ( 61.49 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jun 11 00:43:27 2008
    Info: Elapsed time: 00:00:02