📄 miba.fit.talkback.xml
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<cell_number>2</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>led[3]</name>
<pin__>11</pin__>
<i_o_bank>1</i_o_bank>
<x_coordinate>0</x_coordinate>
<y_coordinate>23</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>led[4]</name>
<pin__>12</pin__>
<i_o_bank>1</i_o_bank>
<x_coordinate>0</x_coordinate>
<y_coordinate>23</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>led[5]</name>
<pin__>13</pin__>
<i_o_bank>1</i_o_bank>
<x_coordinate>0</x_coordinate>
<y_coordinate>23</y_coordinate>
<cell_number>2</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>led[6]</name>
<pin__>14</pin__>
<i_o_bank>1</i_o_bank>
<x_coordinate>0</x_coordinate>
<y_coordinate>22</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>sel[0]</name>
<pin__>16</pin__>
<i_o_bank>1</i_o_bank>
<x_coordinate>0</x_coordinate>
<y_coordinate>22</y_coordinate>
<cell_number>2</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>sel[1]</name>
<pin__>17</pin__>
<i_o_bank>1</i_o_bank>
<x_coordinate>0</x_coordinate>
<y_coordinate>21</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>sel[2]</name>
<pin__>18</pin__>
<i_o_bank>1</i_o_bank>
<x_coordinate>0</x_coordinate>
<y_coordinate>21</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>User</location_assigned_by>
<load>Unspecified</load>
</row>
</output_pins>
<i_o_bank_usage>
<row>
<i_o_bank>1</i_o_bank>
<usage>15 / 44 ( 34 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
<row>
<i_o_bank>2</i_o_bank>
<usage>0 / 42 ( 0 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
<row>
<i_o_bank>3</i_o_bank>
<usage>0 / 45 ( 0 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
<row>
<i_o_bank>4</i_o_bank>
<usage>0 / 42 ( 0 % )</usage>
<vccio_voltage>3.3V</vccio_voltage>
</row>
</i_o_bank_usage>
<advanced_data___general>
<row>
<name>Status Code</name>
<value>0</value>
</row>
<row>
<name>Desired User Slack</name>
<value>0</value>
</row>
<row>
<name>Fit Attempts</name>
<value>1</value>
</row>
</advanced_data___general>
<advanced_data___placement_preparation>
<row>
<name>Auto Fit Point 1 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Mid Wire Use - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Mid Slack - Fit Attempt 1</name>
<value>995006</value>
</row>
<row>
<name>Internal Atom Count - Fit Attempt 1</name>
<value>137</value>
</row>
<row>
<name>LE/ALM Count - Fit Attempt 1</name>
<value>137</value>
</row>
<row>
<name>LAB Count - Fit Attempt 1</name>
<value>24</value>
</row>
<row>
<name>Outputs per Lab - Fit Attempt 1</name>
<value>4.458</value>
</row>
<row>
<name>Inputs per LAB - Fit Attempt 1</name>
<value>5.208</value>
</row>
<row>
<name>Global Inputs per LAB - Fit Attempt 1</name>
<value>0.958</value>
</row>
<row>
<name>LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1</name>
<value>0:24</value>
</row>
<row>
<name>LAB Constraint 'ce + sync load' - Fit Attempt 1</name>
<value>0:21;1:3</value>
</row>
<row>
<name>LAB Constraint 'non-global controls' - Fit Attempt 1</name>
<value>0:21;2:3</value>
</row>
<row>
<name>LAB Constraint 'un-route combination' - Fit Attempt 1</name>
<value>0:21;2:3</value>
</row>
<row>
<name>LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1</name>
<value>0:20;1:1;3:3</value>
</row>
<row>
<name>LAB Constraint 'un-route with async_clear' - Fit Attempt 1</name>
<value>0:20;1:1;3:3</value>
</row>
<row>
<name>LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1</name>
<value>0:21;1:3</value>
</row>
<row>
<name>LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1</name>
<value>0:24</value>
</row>
<row>
<name>LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1</name>
<value>0:21;1:3</value>
</row>
<row>
<name>LAB Constraint 'global control signals' - Fit Attempt 1</name>
<value>0:6;1:14;2:3;3:1</value>
</row>
<row>
<name>LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1</name>
<value>0:6;1:17;2:1</value>
</row>
<row>
<name>LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1</name>
<value>0:24</value>
</row>
<row>
<name>LAB Constraint 'aload_aclr pair' - Fit Attempt 1</name>
<value>0:6;1:17;2:1</value>
</row>
<row>
<name>LAB Constraint 'sload_sclear pair' - Fit Attempt 1</name>
<value>0:17;1:7</value>
</row>
<row>
<name>LAB Constraint 'invert_a constraint' - Fit Attempt 1</name>
<value>0:10;1:14</value>
</row>
<row>
<name>LAB Constraint 'has placement constraint' - Fit Attempt 1</name>
<value>0:20;1:4</value>
</row>
<row>
<name>LEs in Chains - Fit Attempt 1</name>
<value>54</value>
</row>
<row>
<name>LEs in Long Chains - Fit Attempt 1</name>
<value>32</value>
</row>
<row>
<name>LABs with Chains - Fit Attempt 1</name>
<value>7</value>
</row>
<row>
<name>LABs with Multiple Chains - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Time - Fit Attempt 1</name>
<value>0</value>
</row>
</advanced_data___placement_preparation>
<advanced_data___placement>
<row>
<name>Auto Fit Point 2 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Early Wire Use - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Early Slack - Fit Attempt 1</name>
<value>991603</value>
</row>
<row>
<name>Auto Fit Point 3 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Mid Wire Use - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Mid Slack - Fit Attempt 1</name>
<value>993526</value>
</row>
<row>
<name>Auto Fit Point 4 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Late Wire Use - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Late Slack - Fit Attempt 1</name>
<value>993526</value>
</row>
<row>
<name>Auto Fit Point 5 - Fit Attempt 1</name>
<value>ff</value>
</row>
<row>
<name>Time - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Time in tsm_dat.dll - Fit Attempt 1</name>
<value>0.109</value>
</row>
<row>
<name>Time in tsm_tan.dll - Fit Attempt 1</name>
<value>0.156</value>
</row>
</advanced_data___placement>
<advanced_data___routing>
<row>
<name>Early Slack - Fit Attempt 1</name>
<value>993088</value>
</row>
<row>
<name>Early Wire Use - Fit Attempt 1</name>
<value>0</value>
</row>
<row>
<name>Peak Regional Wire - Fit Attempt 1</name>
<value>1</value>
</row>
<row>
<name>Mid Slack - Fit Attempt 1</name>
<value>991500</value>
</row>
<row>
<name>Late Slack - Fit Attempt 1</name>
<value>991500</value>
</row>
<row>
<name>Late Slack - Fit Attempt 1</name>
<value>991500</value>
</row>
<row>
<name>Late Wire Use - Fit Attempt 1</name>
<value>1</value>
</row>
<row>
<name>Time - Fit Attempt 1</name>
<value>1</value>
</row>
<row>
<name>Time in tsm_tan.dll - Fit Attempt 1</name>
<value>0.187</value>
</row>
</advanced_data___routing>
<compilation_summary>
<flow_status>Successful - Wed Jun 11 16:18:12 2008</flow_status>
<quartus_ii_version>5.1 Build 176 10/26/2005 SJ Full Version</quartus_ii_version>
<revision_name>miba</revision_name>
<top_level_entity_name>miba</top_level_entity_name>
<family>Cyclone</family>
<device>EP1C12Q240C8</device>
<timing_models>Final</timing_models>
<met_timing_requirements>N/A</met_timing_requirements>
<total_logic_elements>136 / 12,060 ( 1 % )</total_logic_elements>
<total_pins>13 / 173 ( 8 % )</total_pins>
<total_virtual_pins>0</total_virtual_pins>
<total_memory_bits>0 / 239,616 ( 0 % )</total_memory_bits>
<total_plls>0 / 2 ( 0 % )</total_plls>
</compilation_summary>
<compile_id>C9695EC7</compile_id>
<files>
<top>C:/Documents and Settings/Administrator/桌面/miaobiao/miba.bdf</top>
<extensions>
<ext ext_name="bdf">1</ext>
<ext ext_name="vwf">1</ext>
<ext ext_name="vhd">6</ext>
</extensions>
<sub_files>
<sub_file>C:/Documents and Settings/Administrator/桌面/miaobiao/miba.bdf</sub_file>
<sub_file>C:/Documents and Settings/Administrator/桌面/miaobiao/miba.vwf</sub_file>
<sub_file>C:/Documents and Settings/Administrator/桌面/miaobiao/deled.vhd</sub_file>
<sub_file>C:/Documents and Settings/Administrator/桌面/miaobiao/zhishi.vhd</sub_file>
<sub_file>C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd</sub_file>
<sub_file>C:/Documents and Settings/Administrator/桌面/miaobiao/second.vhd</sub_file>
<sub_file>C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd</sub_file>
<sub_file>C:/Documents and Settings/Administrator/桌面/miaobiao/fenpin.vhd</sub_file>
</sub_files>
</files>
<architecture>
<family>Cyclone</family>
<auto_device>OFF</auto_device>
<device>EP1C12Q240C8</device>
</architecture>
<pkg_io>
<pin_std count="15">LVTTL</pin_std>
</pkg_io>
<research>
<le_sclr>22</le_sclr>
<le_aclr>59</le_aclr>
<le_aload>0</le_aload>
<le_sload>22</le_sload>
<le_inverta>0</le_inverta>
<le_carry_in>40</le_carry_in>
<le_ce>22</le_ce>
<le_clk>59</le_clk>
<le_ce_sload>0</le_ce_sload>
<pin_sclr>0</pin_sclr>
<pin_aclr>0</pin_aclr>
<pin_ce_in>0</pin_ce_in>
<pin_ce_out>0</pin_ce_out>
</research>
</talkback>
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