paobiao.tan.rpt

一个基于FPGA的数字跑表系统的设计

; N/A           ; None        ; -4.797 ns ; PAUSE ; MSL[0]~reg0 ; CLK      ;
; N/A           ; None        ; -4.797 ns ; PAUSE ; MSL[1]~reg0 ; CLK      ;
; N/A           ; None        ; -4.797 ns ; PAUSE ; MSL[3]~reg0 ; CLK      ;
; N/A           ; None        ; -4.797 ns ; PAUSE ; cn1         ; CLK      ;
; N/A           ; None        ; -5.292 ns ; PAUSE ; MSL[2]~reg0 ; CLK      ;
; N/A           ; None        ; -5.628 ns ; PAUSE ; MSH[0]~reg0 ; CLK      ;
; N/A           ; None        ; -5.628 ns ; PAUSE ; MSH[1]~reg0 ; CLK      ;
; N/A           ; None        ; -5.628 ns ; PAUSE ; MSH[3]~reg0 ; CLK      ;
; N/A           ; None        ; -6.052 ns ; PAUSE ; MSH[2]~reg0 ; CLK      ;
+---------------+-------------+-----------+-------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Mon Jun 02 15:31:01 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off paobiao -c paobiao --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "cn2" as buffer
    Info: Detected ripple clock "cn1" as buffer
Info: Clock "CLK" has Internal fmax of 243.61 MHz between source register "ML[1]~reg0" and destination register "MH[3]~reg0" (period= 4.105 ns)
    Info: + Longest register to register delay is 3.844 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X27_Y1_N6; Fanout = 5; REG Node = 'ML[1]~reg0'
        Info: 2: + IC(0.785 ns) + CELL(0.590 ns) = 1.375 ns; Loc. = LC_X28_Y1_N4; Fanout = 4; COMB Node = 'reduce_nor~129'
        Info: 3: + IC(0.430 ns) + CELL(0.442 ns) = 2.247 ns; Loc. = LC_X28_Y1_N5; Fanout = 1; COMB Node = 'MH[3]~121'
        Info: 4: + IC(0.730 ns) + CELL(0.867 ns) = 3.844 ns; Loc. = LC_X28_Y1_N8; Fanout = 4; REG Node = 'MH[3]~reg0'
        Info: Total cell delay = 1.899 ns ( 49.40 % )
        Info: Total interconnect delay = 1.945 ns ( 50.60 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 12.843 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 9; CLK Node = 'CLK'
            Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X8_Y8_N8; Fanout = 10; REG Node = 'cn1'
            Info: 3: + IC(4.057 ns) + CELL(0.935 ns) = 8.119 ns; Loc. = LC_X8_Y14_N8; Fanout = 9; REG Node = 'cn2'
            Info: 4: + IC(4.013 ns) + CELL(0.711 ns) = 12.843 ns; Loc. = LC_X28_Y1_N8; Fanout = 4; REG Node = 'MH[3]~reg0'
            Info: Total cell delay = 4.050 ns ( 31.53 % )
            Info: Total interconnect delay = 8.793 ns ( 68.47 % )
        Info: - Longest clock path from clock "CLK" to source register is 12.843 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 9; CLK Node = 'CLK'
            Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X8_Y8_N8; Fanout = 10; REG Node = 'cn1'
            Info: 3: + IC(4.057 ns) + CELL(0.935 ns) = 8.119 ns; Loc. = LC_X8_Y14_N8; Fanout = 9; REG Node = 'cn2'
            Info: 4: + IC(4.013 ns) + CELL(0.711 ns) = 12.843 ns; Loc. = LC_X27_Y1_N6; Fanout = 5; REG Node = 'ML[1]~reg0'
            Info: Total cell delay = 4.050 ns ( 31.53 % )
            Info: Total interconnect delay = 8.793 ns ( 68.47 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "MSH[2]~reg0" (data pin = "PAUSE", clock pin = "CLK") is 6.104 ns
    Info: + Longest pin to register delay is 8.970 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_39; Fanout = 7; PIN Node = 'PAUSE'
        Info: 2: + IC(5.317 ns) + CELL(0.590 ns) = 7.376 ns; Loc. = LC_X8_Y8_N2; Fanout = 1; COMB Node = 'MSH[2]~132'
        Info: 3: + IC(0.727 ns) + CELL(0.867 ns) = 8.970 ns; Loc. = LC_X9_Y8_N4; Fanout = 5; REG Node = 'MSH[2]~reg0'
        Info: Total cell delay = 2.926 ns ( 32.62 % )
        Info: Total interconnect delay = 6.044 ns ( 67.38 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.903 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 9; CLK Node = 'CLK'
        Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X9_Y8_N4; Fanout = 5; REG Node = 'MSH[2]~reg0'
        Info: Total cell delay = 2.180 ns ( 75.09 % )
        Info: Total interconnect delay = 0.723 ns ( 24.91 % )
Info: tco from clock "CLK" to destination pin "MH[1]" through register "MH[1]~reg0" is 17.111 ns
    Info: + Longest clock path from clock "CLK" to source register is 12.843 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 9; CLK Node = 'CLK'
        Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X8_Y8_N8; Fanout = 10; REG Node = 'cn1'
        Info: 3: + IC(4.057 ns) + CELL(0.935 ns) = 8.119 ns; Loc. = LC_X8_Y14_N8; Fanout = 9; REG Node = 'cn2'
        Info: 4: + IC(4.013 ns) + CELL(0.711 ns) = 12.843 ns; Loc. = LC_X28_Y1_N7; Fanout = 4; REG Node = 'MH[1]~reg0'
        Info: Total cell delay = 4.050 ns ( 31.53 % )
        Info: Total interconnect delay = 8.793 ns ( 68.47 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.044 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X28_Y1_N7; Fanout = 4; REG Node = 'MH[1]~reg0'
        Info: 2: + IC(1.936 ns) + CELL(2.108 ns) = 4.044 ns; Loc. = PIN_97; Fanout = 0; PIN Node = 'MH[1]'
        Info: Total cell delay = 2.108 ns ( 52.13 % )
        Info: Total interconnect delay = 1.936 ns ( 47.87 % )
Info: th for register "MSL[0]~reg0" (data pin = "PAUSE", clock pin = "CLK") is -4.797 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.903 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 9; CLK Node = 'CLK'
        Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X8_Y8_N6; Fanout = 6; REG Node = 'MSL[0]~reg0'
        Info: Total cell delay = 2.180 ns ( 75.09 % )
        Info: Total interconnect delay = 0.723 ns ( 24.91 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.715 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_39; Fanout = 7; PIN Node = 'PAUSE'
        Info: 2: + IC(5.379 ns) + CELL(0.867 ns) = 7.715 ns; Loc. = LC_X8_Y8_N6; Fanout = 6; REG Node = 'MSL[0]~reg0'
        Info: Total cell delay = 2.336 ns ( 30.28 % )
        Info: Total interconnect delay = 5.379 ns ( 69.72 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Mon Jun 02 15:31:01 2008
    Info: Elapsed time: 00:00:01