paobiao.map.rpt

一个基于FPGA的数字跑表系统的设计

; Ignore translate_off and translate_on Synthesis Directives         ; Off          ; Off           ;
; Show Parameter Settings Tables in Synthesis Report                 ; On           ; On            ;
+--------------------------------------------------------------------+--------------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                                            ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------+
; SRC/paobiao.v                    ; yes             ; User Verilog HDL File  ; D:/《FPGA系统设计与实战》初稿光盘/第3章_实战训练3,4,5/实战训练3  数字跑表/SRC/paobiao.v ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Total logic elements            ; 38        ;
; Total combinational functions   ; 26        ;
;     -- Total 4-input functions  ; 20        ;
;     -- Total 3-input functions  ; 3         ;
;     -- Total 2-input functions  ; 3         ;
;     -- Total 1-input functions  ; 0         ;
;     -- Total 0-input functions  ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 26        ;
; I/O pins                        ; 27        ;
; Maximum fan-out node            ; CLR       ;
; Maximum fan-out                 ; 26        ;
; Total fan-out                   ; 202       ;
; Average fan-out                 ; 3.11      ;
+---------------------------------+-----------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |paobiao                   ; 38 (38)     ; 26           ; 0           ; 27   ; 0            ; 12 (12)      ; 12 (12)           ; 14 (14)          ; 0 (0)           ; |paobiao            ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 26    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 26    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 19    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/《FPGA系统设计与实战》初稿光盘/第3章_实战训练3,4,5/实战训练3  数字跑表/paobiao.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Mon Jun 02 15:30:53 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off paobiao -c paobiao
Info: Found 1 design units, including 1 entities, in source file SRC/paobiao.v
    Info: Found entity 1: paobiao
Info: Elaborating entity "paobiao" for the top level hierarchy
Warning: Verilog HDL assignment warning at paobiao.v(14): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at paobiao.v(18): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at paobiao.v(20): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at paobiao.v(21): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at paobiao.v(24): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at paobiao.v(27): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at paobiao.v(28): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at paobiao.v(37): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at paobiao.v(40): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at paobiao.v(42): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at paobiao.v(43): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at paobiao.v(46): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at paobiao.v(49): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at paobiao.v(50): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at paobiao.v(60): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at paobiao.v(62): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at paobiao.v(64): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at paobiao.v(67): truncated value with size 32 to match size of target (4)
Info: Implemented 65 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 24 output pins
    Info: Implemented 38 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings
    Info: Processing ended: Mon Jun 02 15:30:54 2008
    Info: Elapsed time: 00:00:01