alu.hier_info

这是一个用vhdl语言实现的比较完整的ALU,可以用作其他cPU设计的部件

|ALU
a[0] => Mux~7.IN12
a[0] => lpm_add_sub:ALU_ADDER.dataa[0]
a[0] => x~0.DATAB
a[0] => y~6.DATAA
a[0] => y~7.DATAA
a[0] => sla_r[4].DATAA
a[0] => sla_r[3].DATAA
a[0] => sla_r[2].DATAA
a[0] => sla_r[1].DATAA
a[0] => x~8.DATAA
a[0] => x~9.DATAB
a[0] => x~10.DATAA
a[0] => x~17.DATAB
a[0] => r~0.IN1
a[0] => r~8.IN1
a[0] => r~16.IN1
a[0] => Mux~7.IN19
a[1] => lpm_add_sub:ALU_ADDER.dataa[1]
a[1] => x~7.DATAA
a[1] => x~8.DATAB
a[1] => x~16.DATAB
a[1] => x~17.DATAA
a[1] => r~1.IN0
a[1] => r~9.IN0
a[1] => r~17.IN0
a[1] => Mux~6.IN19
a[2] => lpm_add_sub:ALU_ADDER.dataa[2]
a[2] => x~6.DATAA
a[2] => x~7.DATAB
a[2] => x~15.DATAB
a[2] => x~16.DATAA
a[2] => r~2.IN0
a[2] => r~10.IN0
a[2] => r~18.IN0
a[2] => Mux~5.IN19
a[3] => lpm_add_sub:ALU_ADDER.dataa[3]
a[3] => x~5.DATAA
a[3] => x~6.DATAB
a[3] => x~14.DATAB
a[3] => x~15.DATAA
a[3] => r~3.IN0
a[3] => r~11.IN0
a[3] => r~19.IN0
a[3] => Mux~4.IN19
a[4] => lpm_add_sub:ALU_ADDER.dataa[4]
a[4] => x~4.DATAA
a[4] => x~5.DATAB
a[4] => x~13.DATAB
a[4] => x~14.DATAA
a[4] => r~4.IN0
a[4] => r~12.IN0
a[4] => r~20.IN0
a[4] => Mux~3.IN19
a[5] => lpm_add_sub:ALU_ADDER.dataa[5]
a[5] => x~3.DATAA
a[5] => x~4.DATAB
a[5] => x~12.DATAB
a[5] => x~13.DATAA
a[5] => r~5.IN0
a[5] => r~13.IN0
a[5] => r~21.IN0
a[5] => Mux~2.IN19
a[6] => lpm_add_sub:ALU_ADDER.dataa[6]
a[6] => x~2.DATAA
a[6] => x~3.DATAB
a[6] => x~11.DATAB
a[6] => x~12.DATAA
a[6] => r~6.IN0
a[6] => r~14.IN0
a[6] => r~22.IN0
a[6] => Mux~1.IN19
a[7] => Mux~0.IN13
a[7] => lpm_add_sub:ALU_ADDER.dataa[7]
a[7] => x~1.DATAB
a[7] => y~8.DATAA
a[7] => y~9.DATAA
a[7] => sra_r[6].DATAA
a[7] => sra_r[5].DATAA
a[7] => sra_r[4].DATAA
a[7] => sra_r[3].DATAA
a[7] => x~2.DATAB
a[7] => x~9.DATAA
a[7] => x~10.DATAB
a[7] => x~11.DATAA
a[7] => r~7.IN1
a[7] => r~15.IN1
a[7] => r~23.IN1
a[7] => Mux~0.IN19
b[0] => ADDER_in_datab~7.DATAA
b[0] => r~0.IN0
b[0] => r~8.IN0
b[0] => r~16.IN0
b[0] => ADDER_in_datab~7.DATAB
b[0] => ADDER_in_datab[0].DATAB
b[0] => x~10.OUTPUTSELECT
b[0] => x~11.OUTPUTSELECT
b[0] => x~12.OUTPUTSELECT
b[0] => x~13.OUTPUTSELECT
b[0] => x~14.OUTPUTSELECT
b[0] => x~15.OUTPUTSELECT
b[0] => x~16.OUTPUTSELECT
b[0] => x~17.OUTPUTSELECT
b[0] => x~2.OUTPUTSELECT
b[0] => x~3.OUTPUTSELECT
b[0] => x~4.OUTPUTSELECT
b[0] => x~5.OUTPUTSELECT
b[0] => x~6.OUTPUTSELECT
b[0] => x~7.OUTPUTSELECT
b[0] => x~8.OUTPUTSELECT
b[0] => x~9.OUTPUTSELECT
b[0] => x~1.OUTPUTSELECT
b[0] => x~0.OUTPUTSELECT
b[1] => ADDER_in_datab~6.DATAA
b[1] => r~1.IN1
b[1] => r~9.IN1
b[1] => r~17.IN1
b[1] => ADDER_in_datab~6.DATAB
b[1] => ADDER_in_datab[1].DATAB
b[1] => y~18.OUTPUTSELECT
b[1] => y~19.OUTPUTSELECT
b[1] => y~20.OUTPUTSELECT
b[1] => y~21.OUTPUTSELECT
b[1] => y~22.OUTPUTSELECT
b[1] => y~23.OUTPUTSELECT
b[1] => y~24.OUTPUTSELECT
b[1] => y~25.OUTPUTSELECT
b[1] => y~10.OUTPUTSELECT
b[1] => y~11.OUTPUTSELECT
b[1] => y~12.OUTPUTSELECT
b[1] => y~13.OUTPUTSELECT
b[1] => y~14.OUTPUTSELECT
b[1] => y~15.OUTPUTSELECT
b[1] => y~16.OUTPUTSELECT
b[1] => y~17.OUTPUTSELECT
b[1] => y~3.OUTPUTSELECT
b[1] => y~4.OUTPUTSELECT
b[1] => y~6.OUTPUTSELECT
b[1] => y~7.OUTPUTSELECT
b[1] => y~5.OUTPUTSELECT
b[1] => y~8.OUTPUTSELECT
b[1] => y~9.OUTPUTSELECT
b[1] => y~0.OUTPUTSELECT
b[1] => y~1.OUTPUTSELECT
b[1] => y~2.OUTPUTSELECT
b[2] => ADDER_in_datab~5.DATAA
b[2] => r~2.IN1
b[2] => r~10.IN1
b[2] => r~18.IN1
b[2] => ADDER_in_datab~5.DATAB
b[2] => ADDER_in_datab[2].DATAB
b[2] => ror_r[7].OUTPUTSELECT
b[2] => ror_r[6].OUTPUTSELECT
b[2] => ror_r[5].OUTPUTSELECT
b[2] => ror_r[4].OUTPUTSELECT
b[2] => ror_r[3].OUTPUTSELECT
b[2] => ror_r[2].OUTPUTSELECT
b[2] => ror_r[1].OUTPUTSELECT
b[2] => ror_r[0].OUTPUTSELECT
b[2] => rol_r[7].OUTPUTSELECT
b[2] => rol_r[6].OUTPUTSELECT
b[2] => rol_r[5].OUTPUTSELECT
b[2] => rol_r[4].OUTPUTSELECT
b[2] => rol_r[3].OUTPUTSELECT
b[2] => rol_r[2].OUTPUTSELECT
b[2] => rol_r[1].OUTPUTSELECT
b[2] => rol_r[0].OUTPUTSELECT
b[2] => sla_r[7].OUTPUTSELECT
b[2] => sla_r[6].OUTPUTSELECT
b[2] => sla_r[5].OUTPUTSELECT
b[2] => sla_r[4].OUTPUTSELECT
b[2] => sla_r[3].OUTPUTSELECT
b[2] => sla_r[2].OUTPUTSELECT
b[2] => sla_r[1].OUTPUTSELECT
b[2] => srl_r[7].OUTPUTSELECT
b[2] => srl_r[6].OUTPUTSELECT
b[2] => srl_r[5].OUTPUTSELECT
b[2] => srl_r[4].OUTPUTSELECT
b[2] => srl_r[3].OUTPUTSELECT
b[2] => srl_r[2].OUTPUTSELECT
b[2] => srl_r[1].OUTPUTSELECT
b[2] => srl_r[0].OUTPUTSELECT
b[2] => sll_r[7].OUTPUTSELECT
b[2] => sll_r[6].OUTPUTSELECT
b[2] => sll_r[5].OUTPUTSELECT
b[2] => sll_r[4].OUTPUTSELECT
b[2] => sll_r[3].OUTPUTSELECT
b[2] => sll_r[2].OUTPUTSELECT
b[2] => sll_r[1].OUTPUTSELECT
b[2] => sll_r[0].OUTPUTSELECT
b[2] => sra_r[6].OUTPUTSELECT
b[2] => sra_r[5].OUTPUTSELECT
b[2] => sra_r[4].OUTPUTSELECT
b[2] => sra_r[3].OUTPUTSELECT
b[2] => sra_r[2].OUTPUTSELECT
b[2] => sra_r[1].OUTPUTSELECT
b[2] => sra_r[0].OUTPUTSELECT
b[3] => ADDER_in_datab~4.DATAA
b[3] => r~3.IN1
b[3] => r~11.IN1
b[3] => r~19.IN1
b[3] => ADDER_in_datab~4.DATAB
b[3] => ADDER_in_datab[3].DATAB
b[4] => ADDER_in_datab~3.DATAA
b[4] => r~4.IN1
b[4] => r~12.IN1
b[4] => r~20.IN1
b[4] => ADDER_in_datab~3.DATAB
b[4] => ADDER_in_datab[4].DATAB
b[5] => ADDER_in_datab~2.DATAA
b[5] => r~5.IN1
b[5] => r~13.IN1
b[5] => r~21.IN1
b[5] => ADDER_in_datab~2.DATAB
b[5] => ADDER_in_datab[5].DATAB
b[6] => ADDER_in_datab~1.DATAA
b[6] => r~6.IN1
b[6] => r~14.IN1
b[6] => r~22.IN1
b[6] => ADDER_in_datab~1.DATAB
b[6] => ADDER_in_datab[6].DATAB
b[7] => ADDER_in_datab~0.DATAA
b[7] => r~7.IN0
b[7] => r~15.IN0
b[7] => r~23.IN0
b[7] => ADDER_in_datab~0.DATAB
b[7] => ADDER_in_datab[7].DATAB
op[0] => Mux~0.IN5
op[0] => Mux~1.IN5
op[0] => Mux~2.IN5
op[0] => Mux~3.IN5
op[0] => Mux~4.IN5
op[0] => Mux~5.IN5
op[0] => Mux~6.IN5
op[0] => Mux~7.IN5
op[0] => reduce_nor~5.IN2
op[0] => reduce_nor~8.IN2
op[0] => reduce_nor~0.IN2
op[0] => reduce_nor~1.IN2
op[0] => reduce_nor~2.IN2
op[0] => reduce_nor~3.IN2
op[0] => reduce_nor~4.IN2
op[0] => reduce_nor~7.IN2
op[1] => reduce_nor~1.IN3
op[1] => reduce_nor~3.IN3
op[1] => Mux~0.IN4
op[1] => Mux~1.IN4
op[1] => Mux~2.IN4
op[1] => Mux~3.IN4
op[1] => Mux~4.IN4
op[1] => Mux~5.IN4
op[1] => Mux~6.IN4
op[1] => Mux~7.IN4
op[1] => reduce_nor~4.IN3
op[1] => reduce_nor~5.IN3
op[1] => reduce_nor~0.IN3
op[1] => reduce_nor~2.IN3
op[1] => reduce_nor~7.IN3
op[1] => reduce_nor~8.IN3
op[2] => reduce_nor~0.IN1
op[2] => reduce_nor~1.IN1
op[2] => reduce_nor~2.IN1
op[2] => reduce_nor~3.IN1