booth_multiplier.vhd

这是一个用vhdl硬件描述语言实现的乘法器而不是多路选择器

--实验6 Booth乘法器
LIBRARY IEEE;
USE IEEE.Std_logic_1164.ALL;

ENTITY booth_multiplier IS
     GENERIC(k : POSITIVE := 3); --input number word length less one
     PORT( multiplicand : IN    BIT_VECTOR(k DOWNTO 0);
		   multiplier   : IN    BIT_VECTOR(k DOWNTO 0);	
           clock        : IN    BIT; 
           product      : INOUT BIT_VECTOR((2*k + 2) DOWNTO 0);
		   ready        : OUT   BIT
          );
END booth_multiplier;

ARCHITECTURE structural OF booth_multiplier IS
SIGNAL mdreg      : BIT_VECTOR(k DOWNTO 0);
SIGNAL adderout   : BIT_VECTOR(k DOWNTO 0);
SIGNAL carries    : BIT_VECTOR(k DOWNTO 0);
SIGNAL augend     : BIT_VECTOR(k DOWNTO 0);
SIGNAL tcbuffout  : BIT_VECTOR(k DOWNTO 0);
SIGNAL adder_ovfl : BIT;
SIGNAL comp       : BIT;
SIGNAL clr_md     : BIT; 
SIGNAL load_md    : BIT;
SIGNAL clr_pp     : BIT;
SIGNAL load_pp    : BIT;
SIGNAL shift_pp   : BIT;
SIGNAL boostate   : NATURAL RANGE 0 TO 2*(k + 1) :=0;

BEGIN

PROCESS --main clocked process containing all sequential elements
BEGIN
        WAIT UNTIL (clock'EVENT AND clock = '1');

        --register to hold multiplicand during multiplication
        IF clr_md = '1' THEN
                mdreg <= (OTHERS => '0');
        ELSIF load_md = '1' THEN
                mdreg <= multiplicand;
        ELSE
                mdreg <= mdreg;
        END IF;                
       
        --register/shifter accumulates partial product values
        IF clr_pp = '1' THEN
                product <= (OTHERS => '0');
                product((k+1) downto 1) <= multiplier;
        ELSIF load_pp = '1' THEN
                product((2*k + 2) DOWNTO (k + 2)) <= adderout; --add to top half                 
                product((k+1) DOWNTO 0) <= product((k+1) DOWNTO 0);  --refresh bootm half
        ELSIF shift_pp = '1' THEN
                product <= product SRA 1; --shift right with sign extend
        ELSE
                product <= product;
        END IF;

END PROCESS;

--adder adds/subtracts partial product to multiplicand

augend <= product((2*k+2) DOWNTO (k+2));
addgen : FOR i IN adderout'RANGE 
        GENERATE
                lsadder : IF i = 0 GENERATE
                        adderout(i) <= tcbuffout(i) XOR augend(i) XOR product(1);
                        carries(i) <= (tcbuffout(i) AND augend(i)) OR
                                      (tcbuffout(i) AND product(1)) OR
                                      (product(1) AND augend(i));
                        END GENERATE;
                otheradder : IF i /= 0 GENERATE
                        adderout(i) <= tcbuffout(i) XOR augend(i) XOR carries(i-1);
                        carries(i) <= (tcbuffout(i) AND augend(i)) OR
                                      (tcbuffout(i) AND carries(i-1)) OR
                                      (carries(i-1) AND augend(i));
                        END GENERATE;
        END GENERATE;
        --twos comp overflow bit
        adder_ovfl <= carries(k-1) XOR carries(k);

--true/complement buffer to generate two's comp of mdreg
tcbuffout <= NOT mdreg WHEN (product(1)='1') ELSE mdreg;

--booth multiplier state counter
PROCESS BEGIN  
        WAIT UNTIL (clock'EVENT AND clock = '1');
        IF boostate < 2*(k + 1) THEN 
			boostate <= boostate + 1;	
			ready <='0';								 
        ELSE 
			ready <='1';
		    boostate <= 0; 
        END IF;
END PROCESS;

--assign control signal values based on state 
PROCESS(boostate)
BEGIN
        --assign defaults, all registers refresh        
        clr_md <= '0';
        load_md <= '0';
        clr_pp <= '0';
        load_pp <= '0';
        shift_pp <= '0';        
		--boostate <=0;
        IF boostate = 0 THEN
                load_md <= '1';
                clr_pp <= '1';
        ELSIF boostate MOD 2 = 0 THEN   --boostate = 2,4,6,8 ....
                shift_pp <= '1';
        ELSE    --boostate = 1,3,5,7......
                IF product(1) = product(0) THEN
                        NULL; --refresh pp
                ELSE
                        load_pp <= '1'; --update product        
                END IF;                
        END IF;
END PROCESS;

END structural;