booth_multiplier.map.eqn

这是一个用vhdl硬件描述语言实现的乘法器而不是多路选择器

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-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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-- applicable agreement for further details.
--A1L48Q is ready~reg0
--operation mode is normal

A1L48Q_lut_out = C1_q[3];
A1L48Q = DFFEA(A1L48Q_lut_out, clock, , , , , );

--A1L38Q is ready~6
--operation mode is normal

A1L38Q = A1L48Q;


--C1_q[3] is lpm_counter:boostate_rtl_0|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

C1_q[3]_lut_out = (C1_q[3] $ C1L7) & C1L71;
C1_q[3] = DFFEA(C1_q[3]_lut_out, clock, , , , , );

--C1L81Q is lpm_counter:boostate_rtl_0|alt_counter_f10ke:wysi_counter|q[3]~1
--operation mode is clrb_cntr

C1L81Q = C1_q[3];


--C1_q[2] is lpm_counter:boostate_rtl_0|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

C1_q[2]_lut_out = (C1_q[2] $ C1L5) & C1L71;
C1_q[2] = DFFEA(C1_q[2]_lut_out, clock, , , , , );

--C1L51Q is lpm_counter:boostate_rtl_0|alt_counter_f10ke:wysi_counter|q[2]~2
--operation mode is clrb_cntr

C1L51Q = C1_q[2];

--C1L7 is lpm_counter:boostate_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

C1L7 = CARRY(C1_q[2] & (C1L5));


--A1L14Q is product[0]~reg0
--operation mode is normal

A1L14Q_lut_out = A1L58 & (A1L78 & A1L44Q # !A1L78 & (A1L14Q));
A1L14Q = DFFEA(A1L14Q_lut_out, clock, , , , , );

--A1L04Q is product[0]~2522
--operation mode is normal

A1L04Q = A1L14Q;


--A1L44Q is product[1]~reg0
--operation mode is normal

A1L44Q_lut_out = A1L58 & A1L66 # !A1L58 & (multiplier[0]);
A1L44Q = DFFEA(A1L44Q_lut_out, clock, , , , , );

--A1L34Q is product[1]~2523
--operation mode is normal

A1L34Q = A1L44Q;


--A1L74Q is product[2]~reg0
--operation mode is normal

A1L74Q_lut_out = A1L58 & A1L76 # !A1L58 & (multiplier[1]);
A1L74Q = DFFEA(A1L74Q_lut_out, clock, , , , , );

--A1L64Q is product[2]~2524
--operation mode is normal

A1L64Q = A1L74Q;


--A1L05Q is product[3]~reg0
--operation mode is normal

A1L05Q_lut_out = A1L58 & A1L86 # !A1L58 & (multiplier[2]);
A1L05Q = DFFEA(A1L05Q_lut_out, clock, , , , , );

--A1L94Q is product[3]~2525
--operation mode is normal

A1L94Q = A1L05Q;


--A1L35Q is product[4]~reg0
--operation mode is normal

A1L35Q_lut_out = A1L58 & A1L96 # !A1L58 & (multiplier[3]);
A1L35Q = DFFEA(A1L35Q_lut_out, clock, , , , , );

--A1L25Q is product[4]~2526
--operation mode is normal

A1L25Q = A1L35Q;


--A1L65Q is product[5]~reg0
--operation mode is normal

A1L65Q_lut_out = A1L58 & A1L17;
A1L65Q = DFFEA(A1L65Q_lut_out, clock, , , , , );

--A1L55Q is product[5]~2527
--operation mode is normal

A1L55Q = A1L65Q;


--A1L95Q is product[6]~reg0
--operation mode is normal

A1L95Q_lut_out = A1L58 & (A1L27 # A1L51 & adderout[1]);
A1L95Q = DFFEA(A1L95Q_lut_out, clock, , , , , );

--A1L85Q is product[6]~2528
--operation mode is normal

A1L85Q = A1L95Q;


--A1L26Q is product[7]~reg0
--operation mode is normal

A1L26Q_lut_out = A1L58 & (A1L51 & adderout[2] # !A1L51 & (A1L37));
A1L26Q = DFFEA(A1L26Q_lut_out, clock, , , , , );

--A1L16Q is product[7]~2529
--operation mode is normal

A1L16Q = A1L26Q;


--A1L56Q is product[8]~reg0
--operation mode is normal

A1L56Q_lut_out = A1L58 & (A1L51 & adderout[3] # !A1L51 & (A1L56Q));
A1L56Q = DFFEA(A1L56Q_lut_out, clock, , , , , );

--A1L46Q is product[8]~2530
--operation mode is normal

A1L46Q = A1L56Q;


--C1_q[1] is lpm_counter:boostate_rtl_0|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

C1_q[1]_lut_out = (C1_q[1] $ C1L3) & C1L71;
C1_q[1] = DFFEA(C1_q[1]_lut_out, clock, , , , , );

--C1L31Q is lpm_counter:boostate_rtl_0|alt_counter_f10ke:wysi_counter|q[1]~3
--operation mode is clrb_cntr

C1L31Q = C1_q[1];

--C1L5 is lpm_counter:boostate_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

C1L5 = CARRY(C1_q[1] & (C1L3));


--C1_q[0] is lpm_counter:boostate_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

C1_q[0]_lut_out = (!C1_q[0]) & C1L71;
C1_q[0] = DFFEA(C1_q[0]_lut_out, clock, , , , , );

--C1L11Q is lpm_counter:boostate_rtl_0|alt_counter_f10ke:wysi_counter|q[0]~4
--operation mode is clrb_cntr

C1L11Q = C1_q[0];

--C1L3 is lpm_counter:boostate_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

C1L3 = CARRY(C1_q[0]);


--A1L58 is reduce_nor~19
--operation mode is normal

A1L58 = C1_q[3] # C1_q[2] # C1_q[1] # C1_q[0];

--A1L68 is reduce_nor~20
--operation mode is normal

A1L68 = C1_q[3] # C1_q[2] # C1_q[1] # C1_q[0];


--A1L78 is shift_pp~18
--operation mode is normal

A1L78 = !C1_q[0] & (C1_q[3] # C1_q[2] # C1_q[1]);

--A1L88 is shift_pp~19
--operation mode is normal

A1L88 = !C1_q[0] & (C1_q[3] # C1_q[2] # C1_q[1]);


--A1L66 is product~2506
--operation mode is normal

A1L66 = A1L78 & A1L74Q # !A1L78 & (A1L44Q);

--A1L47 is product~2531
--operation mode is normal

A1L47 = A1L78 & A1L74Q # !A1L78 & (A1L44Q);


--A1L76 is product~2508
--operation mode is normal

A1L76 = A1L78 & A1L05Q # !A1L78 & (A1L74Q);

--A1L57 is product~2532
--operation mode is normal

A1L57 = A1L78 & A1L05Q # !A1L78 & (A1L74Q);


--A1L86 is product~2510
--operation mode is normal

A1L86 = A1L78 & A1L35Q # !A1L78 & (A1L05Q);

--A1L67 is product~2533
--operation mode is normal

A1L67 = A1L78 & A1L35Q # !A1L78 & (A1L05Q);


--A1L96 is product~2512
--operation mode is normal

A1L96 = A1L78 & A1L65Q # !A1L78 & (A1L35Q);

--A1L77 is product~2534
--operation mode is normal

A1L77 = A1L78 & A1L65Q # !A1L78 & (A1L35Q);


--A1L51 is load_pp~11
--operation mode is normal

A1L51 = C1_q[0] & (A1L14Q $ A1L44Q);

--A1L61 is load_pp~12
--operation mode is normal

A1L61 = C1_q[0] & (A1L14Q $ A1L44Q);


--A1L07 is product~2514
--operation mode is normal

A1L07 = !A1L51 & (A1L78 & A1L95Q # !A1L78 & (A1L65Q));

--A1L87 is product~2535
--operation mode is normal

A1L87 = !A1L51 & (A1L78 & A1L95Q # !A1L78 & (A1L65Q));


--mdreg[0] is mdreg[0]
--operation mode is normal

mdreg[0]_lut_out = multiplicand[0];
mdreg[0] = DFFEA(mdreg[0]_lut_out, clock, , , A1L91, , );

--A1L02Q is mdreg[0]~8
--operation mode is normal

A1L02Q = mdreg[0];


--A1L17 is product~2515
--operation mode is normal

A1L17 = A1L07 # A1L51 & (A1L65Q $ mdreg[0]);

--A1L97 is product~2536
--operation mode is normal

A1L97 = A1L07 # A1L51 & (A1L65Q $ mdreg[0]);


--A1L27 is product~2517
--operation mode is normal

A1L27 = !A1L51 & (A1L78 & A1L26Q # !A1L78 & (A1L95Q));

--A1L08 is product~2537
--operation mode is normal

A1L08 = !A1L51 & (A1L78 & A1L26Q # !A1L78 & (A1L95Q));


--A1L8 is carries[0]~429
--operation mode is normal

A1L8 = mdreg[0] & A1L65Q # !mdreg[0] & (A1L44Q);

--A1L9 is carries[0]~432
--operation mode is normal

A1L9 = mdreg[0] & A1L65Q # !mdreg[0] & (A1L44Q);


--mdreg[1] is mdreg[1]
--operation mode is normal

mdreg[1]_lut_out = multiplicand[1];
mdreg[1] = DFFEA(mdreg[1]_lut_out, clock, , , A1L91, , );

--A1L32Q is mdreg[1]~9
--operation mode is normal

A1L32Q = mdreg[1];


--adderout[1] is adderout[1]
--operation mode is normal

adderout[1] = A1L95Q $ A1L8 $ A1L44Q $ mdreg[1];

--A1L3 is adderout[1]~257
--operation mode is normal

A1L3 = A1L95Q $ A1L8 $ A1L44Q $ mdreg[1];


--A1L01 is carries[1]~430
--operation mode is normal

A1L01 = A1L95Q & (A1L8 # A1L44Q $ mdreg[1]) # !A1L95Q & A1L8 & (A1L44Q $ mdreg[1]);

--A1L11 is carries[1]~433
--operation mode is normal

A1L11 = A1L95Q & (A1L8 # A1L44Q $ mdreg[1]) # !A1L95Q & A1L8 & (A1L44Q $ mdreg[1]);


--mdreg[2] is mdreg[2]
--operation mode is normal

mdreg[2]_lut_out = multiplicand[2];
mdreg[2] = DFFEA(mdreg[2]_lut_out, clock, , , A1L91, , );

--A1L52Q is mdreg[2]~10
--operation mode is normal

A1L52Q = mdreg[2];


--adderout[2] is adderout[2]
--operation mode is normal

adderout[2] = A1L01 $ A1L26Q $ A1L44Q $ mdreg[2];

--A1L5 is adderout[2]~258
--operation mode is normal

A1L5 = A1L01 $ A1L26Q $ A1L44Q $ mdreg[2];


--A1L37 is product~2519
--operation mode is normal

A1L37 = A1L78 & A1L56Q # !A1L78 & (A1L26Q);

--A1L18 is product~2538
--operation mode is normal

A1L18 = A1L78 & A1L56Q # !A1L78 & (A1L26Q);


--A1L21 is carries[2]~431
--operation mode is normal

A1L21 = A1L26Q & (A1L01 # A1L44Q $ mdreg[2]) # !A1L26Q & A1L01 & (A1L44Q $ mdreg[2]);

--A1L31 is carries[2]~434
--operation mode is normal

A1L31 = A1L26Q & (A1L01 # A1L44Q $ mdreg[2]) # !A1L26Q & A1L01 & (A1L44Q $ mdreg[2]);


--mdreg[3] is mdreg[3]
--operation mode is normal

mdreg[3]_lut_out = multiplicand[3];
mdreg[3] = DFFEA(mdreg[3]_lut_out, clock, , , A1L91, , );

--A1L72Q is mdreg[3]~11
--operation mode is normal

A1L72Q = mdreg[3];


--adderout[3] is adderout[3]
--operation mode is normal

adderout[3] = A1L21 $ A1L44Q $ A1L56Q $ mdreg[3];

--A1L7 is adderout[3]~259
--operation mode is normal

A1L7 = A1L21 $ A1L44Q $ A1L56Q $ mdreg[3];


--A1L91 is mdreg[0]~4
--operation mode is normal

A1L91 = !A1L58;

--A1L12 is mdreg[0]~12
--operation mode is normal

A1L12 = !A1L58;


--clock is clock
--operation mode is input

clock = INPUT();


--multiplier[0] is multiplier[0]
--operation mode is input

multiplier[0] = INPUT();


--multiplier[1] is multiplier[1]
--operation mode is input

multiplier[1] = INPUT();


--multiplier[2] is multiplier[2]
--operation mode is input

multiplier[2] = INPUT();


--multiplier[3] is multiplier[3]
--operation mode is input

multiplier[3] = INPUT();


--multiplicand[0] is multiplicand[0]
--operation mode is input

multiplicand[0] = INPUT();


--multiplicand[1] is multiplicand[1]
--operation mode is input

multiplicand[1] = INPUT();


--multiplicand[2] is multiplicand[2]
--operation mode is input

multiplicand[2] = INPUT();


--multiplicand[3] is multiplicand[3]
--operation mode is input

multiplicand[3] = INPUT();


--ready is ready
--operation mode is output

ready = OUTPUT(A1L48Q);


--product[0] is product[0]
--operation mode is bidir

product[0]_tri_out = TRI(A1L14Q, VCC);
product[0] = BIDIR(product[0]_tri_out);


--product[1] is product[1]
--operation mode is bidir

product[1]_tri_out = TRI(A1L44Q, VCC);
product[1] = BIDIR(product[1]_tri_out);


--product[2] is product[2]
--operation mode is bidir

product[2]_tri_out = TRI(A1L74Q, VCC);
product[2] = BIDIR(product[2]_tri_out);


--product[3] is product[3]
--operation mode is bidir

product[3]_tri_out = TRI(A1L05Q, VCC);
product[3] = BIDIR(product[3]_tri_out);


--product[4] is product[4]
--operation mode is bidir

product[4]_tri_out = TRI(A1L35Q, VCC);
product[4] = BIDIR(product[4]_tri_out);


--product[5] is product[5]
--operation mode is bidir

product[5]_tri_out = TRI(A1L65Q, VCC);
product[5] = BIDIR(product[5]_tri_out);


--product[6] is product[6]
--operation mode is bidir

product[6]_tri_out = TRI(A1L95Q, VCC);
product[6] = BIDIR(product[6]_tri_out);


--product[7] is product[7]
--operation mode is bidir

product[7]_tri_out = TRI(A1L26Q, VCC);
product[7] = BIDIR(product[7]_tri_out);


--product[8] is product[8]
--operation mode is bidir

product[8]_tri_out = TRI(A1L56Q, VCC);
product[8] = BIDIR(product[8]_tri_out);


--C1L71 is lpm_counter:boostate_rtl_0|alt_counter_f10ke:wysi_counter|q[3]~0
--operation mode is normal

C1L71 = !C1_q[3];