booth_multiplier.tan.rpt

这是一个用vhdl硬件描述语言实现的乘法器而不是多路选择器

+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Aug 23 16:23:27 2005
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off booth_multiplier -c booth_multiplier
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" has Internal fmax of 75.19 MHz between source register "mdreg[0]" and destination register "product[8]~reg0" (period= 13.3 ns)
    Info: + Longest register to register delay is 11.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C31; Fanout = 2; REG Node = 'mdreg[0]'
        Info: 2: + IC(1.100 ns) + CELL(2.000 ns) = 3.100 ns; Loc. = LC7_C33; Fanout = 2; COMB Node = 'carries[0]~429'
        Info: 3: + IC(0.200 ns) + CELL(1.900 ns) = 5.200 ns; Loc. = LC2_C33; Fanout = 2; COMB Node = 'carries[1]~430'
        Info: 4: + IC(1.100 ns) + CELL(1.900 ns) = 8.200 ns; Loc. = LC6_C34; Fanout = 1; COMB Node = 'carries[2]~431'
        Info: 5: + IC(0.200 ns) + CELL(1.700 ns) = 10.100 ns; Loc. = LC8_C34; Fanout = 1; COMB Node = 'adderout[3]'
        Info: 6: + IC(0.200 ns) + CELL(1.200 ns) = 11.500 ns; Loc. = LC1_C34; Fanout = 4; REG Node = 'product[8]~reg0'
        Info: Total cell delay = 8.700 ns ( 75.65 % )
        Info: Total interconnect delay = 2.800 ns ( 24.35 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clock" to destination register is 1.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 19; CLK Node = 'clock'
            Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_C34; Fanout = 4; REG Node = 'product[8]~reg0'
            Info: Total cell delay = 0.500 ns ( 26.32 % )
            Info: Total interconnect delay = 1.400 ns ( 73.68 % )
        Info: - Longest clock path from clock "clock" to source register is 1.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 19; CLK Node = 'clock'
            Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_C31; Fanout = 2; REG Node = 'mdreg[0]'
            Info: Total cell delay = 0.500 ns ( 26.32 % )
            Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 0.700 ns
Info: tsu for register "product[2]~reg0" (data pin = "multiplier[1]", clock pin = "clock") is 7.900 ns
    Info: + Longest pin to register delay is 9.100 ns
        Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_54; Fanout = 1; PIN Node = 'multiplier[1]'
        Info: 2: + IC(4.800 ns) + CELL(1.200 ns) = 9.100 ns; Loc. = LC4_C32; Fanout = 3; REG Node = 'product[2]~reg0'
        Info: Total cell delay = 4.300 ns ( 47.25 % )
        Info: Total interconnect delay = 4.800 ns ( 52.75 % )
    Info: + Micro setup delay of destination is 0.700 ns
    Info: - Shortest clock path from clock "clock" to destination register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 19; CLK Node = 'clock'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_C32; Fanout = 3; REG Node = 'product[2]~reg0'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
Info: tco from clock "clock" to destination pin "ready" through register "ready~reg0" is 14.700 ns
    Info: + Longest clock path from clock "clock" to source register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 19; CLK Node = 'clock'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_C27; Fanout = 1; REG Node = 'ready~reg0'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 11.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C27; Fanout = 1; REG Node = 'ready~reg0'
        Info: 2: + IC(3.100 ns) + CELL(8.600 ns) = 11.700 ns; Loc. = PIN_120; Fanout = 0; PIN Node = 'ready'
        Info: Total cell delay = 8.600 ns ( 73.50 % )
        Info: Total interconnect delay = 3.100 ns ( 26.50 % )
Info: th for register "mdreg[3]" (data pin = "multiplicand[3]", clock pin = "clock") is -5.100 ns
    Info: + Longest clock path from clock "clock" to destination register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 19; CLK Node = 'clock'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_C31; Fanout = 1; REG Node = 'mdreg[3]'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro hold delay of destination is 0.900 ns
    Info: - Shortest pin to register delay is 7.900 ns
        Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_70; Fanout = 1; PIN Node = 'multiplicand[3]'
        Info: 2: + IC(3.800 ns) + CELL(1.000 ns) = 7.900 ns; Loc. = LC4_C31; Fanout = 1; REG Node = 'mdreg[3]'
        Info: Total cell delay = 4.100 ns ( 51.90 % )
        Info: Total interconnect delay = 3.800 ns ( 48.10 % )
Info: Minimum tco from clock "clock" to destination pin "product[6]" through register "product[6]~reg0" is 12.400 ns
    Info: + Shortest clock path from clock "clock" to source register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 19; CLK Node = 'clock'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC3_C34; Fanout = 5; REG Node = 'product[6]~reg0'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Shortest register to pin delay is 9.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C34; Fanout = 5; REG Node = 'product[6]~reg0'
        Info: 2: + IC(0.800 ns) + CELL(8.600 ns) = 9.400 ns; Loc. = PIN_14; Fanout = 0; PIN Node = 'product[6]'
        Info: Total cell delay = 8.600 ns ( 91.49 % )
        Info: Total interconnect delay = 0.800 ns ( 8.51 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Aug 23 16:23:28 2005
    Info: Elapsed time: 00:00:02