divider.map.summary

来自「一个用vhdl硬件描述语言实现的一个比较简单的除法器」· SUMMARY 代码 · 共 13 行

Flow Status : Successful - Tue Aug 23 16:25:45 2005
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : divider
Top-level Entity Name : divider
Family : ACEX1K
Device : EP1K100QC208-3
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 46
Total pins : 27
Total memory bits : 0
Total PLLs : 0