adder8.map.qmsg

实现十六位加法器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 07 10:42:04 2005 " "Info: Processing started: Wed Sep 07 10:42:04 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adder8 -c adder8 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder8 -c adder8" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fulladder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fulladder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fulladder-fulladder_behav " "Info: Found design unit 1: fulladder-fulladder_behav" {  } { { "fulladder.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/fulladder.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 fulladder " "Info: Found entity 1: fulladder" {  } { { "fulladder.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/fulladder.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file adder8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adder8-ripple " "Info: Found design unit 1: adder8-ripple" {  } { { "adder8.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/adder8.vhd" 17 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 adder8 " "Info: Found entity 1: adder8" {  } { { "adder8.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/adder8.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "adder8 " "Info: Elaborating entity \"adder8\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fulladder fulladder:f0 " "Info: Elaborating entity \"fulladder\" for hierarchy \"fulladder:f0\"" {  } { { "adder8.vhd" "f0" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/1.5 运算器部件实验：加法器/adder8.vhd" 27 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "42 " "Info: Implemented 42 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "17 " "Info: Implemented 17 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "16 " "Info: Implemented 16 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 07 10:42:06 2005 " "Info: Processing ended: Wed Sep 07 10:42:06 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}