adder8.fit.summary

实现十六位加法器

Flow Status : Successful - Wed Sep 07 10:42:20 2005
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : adder8
Top-level Entity Name : adder8
Family : ACEX1K
Device : EP1K100QC208-3
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 16 / 4,992 ( < 1 % )
Total pins : 26 / 147 ( 17 % )
Total memory bits : 0 / 49,152 ( 0 % )
Total PLLs : 0