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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--E3_cs_buffer[0] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]
--operation mode is arithmetic
E3_cs_buffer[0] = b[0] $ a[0];
--E3L8 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~97
--operation mode is arithmetic
E3L8 = b[0] $ a[0];
--E3_cout[0] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic
E3_cout[0] = CARRY(b[0] & a[0]);
--E3_cs_buffer[2] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic
E3_cs_buffer[2] = a[2] $ b[2] $ E3_cout[1];
--E3L21 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~98
--operation mode is arithmetic
E3L21 = a[2] $ b[2] $ E3_cout[1];
--E3_cout[2] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic
E3_cout[2] = CARRY(a[2] & (b[2] # E3_cout[1]) # !a[2] & b[2] & E3_cout[1]);
--E3_cs_buffer[3] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic
E3_cs_buffer[3] = a[3] $ b[3] $ E3_cout[2];
--E3L41 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~99
--operation mode is arithmetic
E3L41 = a[3] $ b[3] $ E3_cout[2];
--E3_cout[3] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic
E3_cout[3] = CARRY(a[3] & (b[3] # E3_cout[2]) # !a[3] & b[3] & E3_cout[2]);
--E3_cs_buffer[1] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic
E3_cs_buffer[1] = a[1] $ b[1] $ E3_cout[0];
--E3L01 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~100
--operation mode is arithmetic
E3L01 = a[1] $ b[1] $ E3_cout[0];
--E3_cout[1] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic
E3_cout[1] = CARRY(a[1] & (b[1] # E3_cout[0]) # !a[1] & b[1] & E3_cout[0]);
--A1L91 is sum~194
--operation mode is normal
A1L91 = C1_unreg_res_node[4] & (!E3_cs_buffer[1]) # !C1_unreg_res_node[4] & (E3_cs_buffer[3] & E3_cs_buffer[2] & !E3_cs_buffer[1] # !E3_cs_buffer[3] & (E3_cs_buffer[1]));
--A1L32 is sum~198
--operation mode is normal
A1L32 = C1_unreg_res_node[4] & (!E3_cs_buffer[1]) # !C1_unreg_res_node[4] & (E3_cs_buffer[3] & E3_cs_buffer[2] & !E3_cs_buffer[1] # !E3_cs_buffer[3] & (E3_cs_buffer[1]));
--A1L02 is sum~195
--operation mode is normal
A1L02 = E3_cs_buffer[2] & (E3_cs_buffer[1] # !C1_unreg_res_node[4] & !E3_cs_buffer[3]) # !E3_cs_buffer[2] & !E3_cs_buffer[1] & C1_unreg_res_node[4];
--A1L42 is sum~199
--operation mode is normal
A1L42 = E3_cs_buffer[2] & (E3_cs_buffer[1] # !C1_unreg_res_node[4] & !E3_cs_buffer[3]) # !E3_cs_buffer[2] & !E3_cs_buffer[1] & C1_unreg_res_node[4];
--A1L12 is sum~196
--operation mode is normal
A1L12 = E3_cs_buffer[3] & (!E3_cs_buffer[1] & !E3_cs_buffer[2]) # !E3_cs_buffer[3] & C1_unreg_res_node[4] & (E3_cs_buffer[1] # E3_cs_buffer[2]);
--A1L52 is sum~200
--operation mode is normal
A1L52 = E3_cs_buffer[3] & (!E3_cs_buffer[1] & !E3_cs_buffer[2]) # !E3_cs_buffer[3] & C1_unreg_res_node[4] & (E3_cs_buffer[1] # E3_cs_buffer[2]);
--A1L22 is sum~197
--operation mode is normal
A1L22 = C1_unreg_res_node[4] $ (!E3_cs_buffer[1] & !E3_cs_buffer[2] # !E3_cs_buffer[3]);
--A1L62 is sum~201
--operation mode is normal
A1L62 = C1_unreg_res_node[4] $ (!E3_cs_buffer[1] & !E3_cs_buffer[2] # !E3_cs_buffer[3]);
--C1_unreg_res_node[4] is lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[4]
--operation mode is normal
C1_unreg_res_node[4] = a[4] $ b[4] $ E3_cout[3];
--C1L3 is lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[4]~14
--operation mode is normal
C1L3 = a[4] $ b[4] $ E3_cout[3];
--b[4] is b[4]
--operation mode is input
b[4] = INPUT();
--a[4] is a[4]
--operation mode is input
a[4] = INPUT();
--b[0] is b[0]
--operation mode is input
b[0] = INPUT();
--a[0] is a[0]
--operation mode is input
a[0] = INPUT();
--a[2] is a[2]
--operation mode is input
a[2] = INPUT();
--b[2] is b[2]
--operation mode is input
b[2] = INPUT();
--a[3] is a[3]
--operation mode is input
a[3] = INPUT();
--b[3] is b[3]
--operation mode is input
b[3] = INPUT();
--a[1] is a[1]
--operation mode is input
a[1] = INPUT();
--b[1] is b[1]
--operation mode is input
b[1] = INPUT();
--c[0] is c[0]
--operation mode is output
c[0] = OUTPUT(E3_cs_buffer[0]);
--c[1] is c[1]
--operation mode is output
c[1] = OUTPUT(A1L91);
--c[2] is c[2]
--operation mode is output
c[2] = OUTPUT(A1L02);
--c[3] is c[3]
--operation mode is output
c[3] = OUTPUT(A1L12);
--c[4] is c[4]
--operation mode is output
c[4] = OUTPUT(!A1L22);
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