bcd.vhd

来自「实现BCD码的加法」· VHDL 代码 · 共 26 行

--实验3
--BCD码的加法运算

LIBRARY IEEE;  
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY bcd IS
  PORT( a : UNSIGNED(4 DOWNTO 0);
        b : UNSIGNED(4 DOWNTO 0);        
        c : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
       );
END bcd;

ARCHITECTURE adding OF bcd IS
  SIGNAL sum : STD_LOGIC_VECTOR(4 DOWNTO 0); 
  SIGNAL co  : STD_LOGIC;
  SIGNAL add : integer RANGE 0 TO 31;
BEGIN
  add <= conv_integer(a+b);
  co <= '1' WHEN add>9 ELSE 
        '0';
  sum <= a+b+6 WHEN co='1' ELSE 
         a+b;
  c <= sum;   
END adding;