signal.sim.rpt

来自「yong VerilogHDL yu yan bianxie de pinlv 」· RPT 代码 · 共 307 行 · 第 1/5 页

; Simulation mode                                                                            ; Timing     ; Timing        ;
; Start time                                                                                 ; 0 ns       ; 0 ns          ;
; Simulation results format                                                                  ; CVWF       ;               ;
; Add pins automatically to simulation output waveforms                                      ; On         ; On            ;
; Check outputs                                                                              ; Off        ; Off           ;
; Report simulation coverage                                                                 ; On         ; On            ;
; Display complete 1/0 value coverage report                                                 ; On         ; On            ;
; Display missing 1-value coverage report                                                    ; On         ; On            ;
; Display missing 0-value coverage report                                                    ; On         ; On            ;
; Detect setup and hold time violations                                                      ; Off        ; Off           ;
; Detect glitches                                                                            ; Off        ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off        ; Off           ;
; Generate Signal Activity File                                                              ; Off        ; Off           ;
; Generate VCD File for PowerPlay Power Analyzer                                             ; Off        ; Off           ;
; Group bus channels in simulation results                                                   ; Off        ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On         ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off        ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off        ;               ;
; Perform Glitch Filtering in Timing Simulation                                              ; Auto       ; Auto          ;
+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+----------------------------------------------------------------------------------------------------------------------------+
; |signal|signal_gene:si|datarom:datarom_component|altsyncram:altsyncram_component|altsyncram_ki31:auto_generated|ALTSYNCRAM ;
+----------------------------------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      25.27 % ;
; Total nodes checked                                 ; 242          ;
; Total output ports checked                          ; 368          ;
; Total output ports with complete 1/0-value coverage ; 93           ;
; Total output ports with no 1/0-value coverage       ; 242          ;
; Total output ports with no 1-value coverage         ; 249          ;
; Total output ports with no 0-value coverage         ; 268          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                                                              ;
+------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                                    ; Output Port Name                                                                                                       ; Output Port Type ;
+------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+------------------+
; |signal|signal_gene:si|datarom:datarom_component|altsyncram:altsyncram_component|altsyncram_ki31:auto_generated|ram_block1a0 ; |signal|signal_gene:si|datarom:datarom_component|altsyncram:altsyncram_component|altsyncram_ki31:auto_generated|q_a[1] ; portadataout1    ;
; |signal|signal_gene:si|datarom:datarom_component|altsyncram:altsyncram_component|altsyncram_ki31:auto_generated|ram_block1a0 ; |signal|signal_gene:si|datarom:datarom_component|altsyncram:altsyncram_component|altsyncram_ki31:auto_generated|q_a[2] ; portadataout2    ;
; |signal|signal_gene:si|datarom:datarom_component|altsyncram:altsyncram_component|altsyncram_ki31:auto_generated|ram_block1a0 ; |signal|signal_gene:si|datarom:datarom_component|altsyncram:altsyncram_component|altsyncram_ki31:auto_generated|q_a[3] ; portadataout3    ;
; |signal|signal_gene:si|datarom:datarom_component|altsyncram:altsyncram_component|altsyncram_ki31:auto_generated|ram_block1a0 ; |signal|signal_gene:si|datarom:datarom_component|altsyncram:altsyncram_component|altsyncram_ki31:auto_generated|q_a[4] ; portadataout4    ;