signal.cdf

来自「yong VerilogHDL yu yan bianxie de pinlv 」· CDF 代码 · 共 14 行

/* Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version */
JedecChain;
	FileRevision(JESD32A);
	DefaultMfr(6E);

	P ActionCode(Cfg)
		Device PartName(EPCS1) Path("D:/Project/signal/") File("signal.pof") MfrSpec(OpMask(7) Child_OpMask(1 7));

ChainEnd;

AlteraBegin;
	ChainType(asc);
AlteraEnd;