top.v

yong VerilogHDL yu yan bianxie de pinlv fa sheng qi,shi yong ISE ruan jian da kai.

//`include "signal.v"
//`include "oclk.v"

module top(clk,rst,q_out);
    input clk,rst;
    output[7:0] q_out;
    wire clk1khz;
    
    signal sig(.clkin(clk1khz),.rst(rst),.q_out(q_out));
    oclk    oc(.clk(clk),.rst(rst),.clkout(clk1khz));
endmodule