signal.fit.qmsg

yong VerilogHDL yu yan bianxie de pinlv fa sheng qi,shi yong ISE ruan jian da kai.

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "7.705 ns register register " "Info: Estimated most critical path is register to register delay of 7.705 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns signal_gene:si\|m\[0\] 1 REG LAB_X15_Y6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y6; Fanout = 3; REG Node = 'signal_gene:si\|m\[0\]'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { signal_gene:si|m[0] } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.408 ns) + CELL(0.340 ns) 0.748 ns signal_gene:si\|LessThan2~644 2 COMB LAB_X16_Y6 1 " "Info: 2: + IC(0.408 ns) + CELL(0.340 ns) = 0.748 ns; Loc. = LAB_X16_Y6; Fanout = 1; COMB Node = 'signal_gene:si\|LessThan2~644'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.748 ns" { signal_gene:si|m[0] signal_gene:si|LessThan2~644 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.278 ns) + CELL(0.225 ns) 1.251 ns signal_gene:si\|LessThan2~645 3 COMB LAB_X16_Y6 1 " "Info: 3: + IC(0.278 ns) + CELL(0.225 ns) = 1.251 ns; Loc. = LAB_X16_Y6; Fanout = 1; COMB Node = 'signal_gene:si\|LessThan2~645'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.503 ns" { signal_gene:si|LessThan2~644 signal_gene:si|LessThan2~645 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.278 ns) + CELL(0.225 ns) 1.754 ns signal_gene:si\|LessThan2~646 4 COMB LAB_X16_Y6 1 " "Info: 4: + IC(0.278 ns) + CELL(0.225 ns) = 1.754 ns; Loc. = LAB_X16_Y6; Fanout = 1; COMB Node = 'signal_gene:si\|LessThan2~646'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.503 ns" { signal_gene:si|LessThan2~645 signal_gene:si|LessThan2~646 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.278 ns) + CELL(0.225 ns) 2.257 ns signal_gene:si\|LessThan2~650 5 COMB LAB_X16_Y6 1 " "Info: 5: + IC(0.278 ns) + CELL(0.225 ns) = 2.257 ns; Loc. = LAB_X16_Y6; Fanout = 1; COMB Node = 'signal_gene:si\|LessThan2~650'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.503 ns" { signal_gene:si|LessThan2~646 signal_gene:si|LessThan2~650 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.278 ns) + CELL(0.225 ns) 2.760 ns signal_gene:si\|LessThan2~647 6 COMB LAB_X16_Y6 1 " "Info: 6: + IC(0.278 ns) + CELL(0.225 ns) = 2.760 ns; Loc. = LAB_X16_Y6; Fanout = 1; COMB Node = 'signal_gene:si\|LessThan2~647'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.503 ns" { signal_gene:si|LessThan2~650 signal_gene:si|LessThan2~647 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.278 ns) + CELL(0.225 ns) 3.263 ns signal_gene:si\|LessThan2~648 7 COMB LAB_X16_Y6 1 " "Info: 7: + IC(0.278 ns) + CELL(0.225 ns) = 3.263 ns; Loc. = LAB_X16_Y6; Fanout = 1; COMB Node = 'signal_gene:si\|LessThan2~648'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.503 ns" { signal_gene:si|LessThan2~647 signal_gene:si|LessThan2~648 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.278 ns) + CELL(0.225 ns) 3.766 ns signal_gene:si\|LessThan2~649 8 COMB LAB_X16_Y6 2 " "Info: 8: + IC(0.278 ns) + CELL(0.225 ns) = 3.766 ns; Loc. = LAB_X16_Y6; Fanout = 2; COMB Node = 'signal_gene:si\|LessThan2~649'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.503 ns" { signal_gene:si|LessThan2~648 signal_gene:si|LessThan2~649 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.088 ns) 4.269 ns signal_gene:si\|address\[4\]~1327 9 COMB LAB_X16_Y6 1 " "Info: 9: + IC(0.415 ns) + CELL(0.088 ns) = 4.269 ns; Loc. = LAB_X16_Y6; Fanout = 1; COMB Node = 'signal_gene:si\|address\[4\]~1327'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.503 ns" { signal_gene:si|LessThan2~649 signal_gene:si|address[4]~1327 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.088 ns) 4.772 ns signal_gene:si\|address\[4\]~1328 10 COMB LAB_X16_Y6 1 " "Info: 10: + IC(0.415 ns) + CELL(0.088 ns) = 4.772 ns; Loc. = LAB_X16_Y6; Fanout = 1; COMB Node = 'signal_gene:si\|address\[4\]~1328'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.503 ns" { signal_gene:si|address[4]~1327 signal_gene:si|address[4]~1328 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.636 ns) + CELL(0.340 ns) 5.748 ns signal_gene:si\|address\[4\]~1330 11 COMB LAB_X18_Y6 1 " "Info: 11: + IC(0.636 ns) + CELL(0.340 ns) = 5.748 ns; Loc. = LAB_X18_Y6; Fanout = 1; COMB Node = 'signal_gene:si\|address\[4\]~1330'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.976 ns" { signal_gene:si|address[4]~1328 signal_gene:si|address[4]~1330 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.460 ns) + CELL(0.225 ns) 6.433 ns signal_gene:si\|address\[4\]~1335 12 COMB LAB_X17_Y6 9 " "Info: 12: + IC(0.460 ns) + CELL(0.225 ns) = 6.433 ns; Loc. = LAB_X17_Y6; Fanout = 9; COMB Node = 'signal_gene:si\|address\[4\]~1335'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.685 ns" { signal_gene:si|address[4]~1330 signal_gene:si|address[4]~1335 } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.329 ns) + CELL(0.943 ns) 7.705 ns signal_gene:si\|address\[0\] 13 REG LAB_X17_Y6 15 " "Info: 13: + IC(0.329 ns) + CELL(0.943 ns) = 7.705 ns; Loc. = LAB_X17_Y6; Fanout = 15; REG Node = 'signal_gene:si\|address\[0\]'" {  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.272 ns" { signal_gene:si|address[4]~1335 signal_gene:si|address[0] } "NODE_NAME" } } { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.374 ns ( 43.79 % ) " "Info: Total cell delay = 3.374 ns ( 43.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.331 ns ( 56.21 % ) " "Info: Total interconnect delay = 4.331 ns ( 56.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.705 ns" { signal_gene:si|m[0] signal_gene:si|LessThan2~644 signal_gene:si|LessThan2~645 signal_gene:si|LessThan2~646 signal_gene:si|LessThan2~650 signal_gene:si|LessThan2~647 signal_gene:si|LessThan2~648 signal_gene:si|LessThan2~649 signal_gene:si|address[4]~1327 signal_gene:si|address[4]~1328 signal_gene:si|address[4]~1330 signal_gene:si|address[4]~1335 signal_gene:si|address[0] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Info: Average interconnect usage is 2% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "3 X14_Y0 X27_Y14 " "Info: Peak interconnect usage is 3% of the available device resources in the region that extends from location X14_Y0 to location X27_Y14" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "4 " "Warning: Following 4 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dataout\[0\] VCC " "Info: Pin dataout\[0\] has VCC driving its datain port" {  } { { "e:/quartus7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/quartus7.2/quartus/bin/pin_planner.ppl" { dataout[0] } } } { "e:/quartus7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "dataout\[0\]" } } } } { "signal.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal.v" 9 -1 0 } } { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { dataout[0] } "NODE_NAME" } } { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { dataout[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dataout\[1\] VCC " "Info: Pin dataout\[1\] has VCC driving its datain port" {  } { { "e:/quartus7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/quartus7.2/quartus/bin/pin_planner.ppl" { dataout[1] } } } { "e:/quartus7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "dataout\[1\]" } } } } { "signal.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal.v" 9 -1 0 } } { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { dataout[1] } "NODE_NAME" } } { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { dataout[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dataout\[5\] GND " "Info: Pin dataout\[5\] has GND driving its datain port" {  } { { "e:/quartus7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/quartus7.2/quartus/bin/pin_planner.ppl" { dataout[5] } } } { "e:/quartus7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "dataout\[5\]" } } } } { "signal.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal.v" 9 -1 0 } } { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { dataout[5] } "NODE_NAME" } } { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { dataout[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dataout\[6\] GND " "Info: Pin dataout\[6\] has GND driving its datain port" {  } { { "e:/quartus7.2/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/quartus7.2/quartus/bin/pin_planner.ppl" { dataout[6] } } } { "e:/quartus7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "dataout\[6\]" } } } } { "signal.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal.v" 9 -1 0 } } { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { dataout[6] } "NODE_NAME" } } { "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { dataout[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/Electronic/Quartus 7.2/EX/Signal/signal.fit.smsg " "Info: Generated suppressed messages file D:/Electronic/Quartus 7.2/EX/Signal/signal.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "170 " "Info: Allocated 170 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jun 07 13:50:27 2008 " "Info: Processing ended: Sat Jun 07 13:50:27 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}