signal.map.qmsg

yong VerilogHDL yu yan bianxie de pinlv fa sheng qi,shi yong ISE ruan jian da kai.

{ "Warning" "WSGN_SEARCH_FILE" "datarom.v 1 1 " "Warning: Using design file datarom.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 datarom " "Info: Found entity 1: datarom" {  } { { "datarom.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/datarom.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "datarom signal_gene:si\|datarom:datarom_component " "Info: Elaborating entity \"datarom\" for hierarchy \"signal_gene:si\|datarom:datarom_component\"" {  } { { "signal_gene.v" "datarom_component" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 9 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus7.2/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/quartus7.2/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "e:/quartus7.2/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram signal_gene:si\|datarom:datarom_component\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"signal_gene:si\|datarom:datarom_component\|altsyncram:altsyncram_component\"" {  } { { "datarom.v" "altsyncram_component" { Text "D:/Electronic/Quartus 7.2/EX/Signal/datarom.v" 74 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "signal_gene:si\|datarom:datarom_component\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"signal_gene:si\|datarom:datarom_component\|altsyncram:altsyncram_component\"" {  } { { "datarom.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/datarom.v" 74 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ki31.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ki31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ki31 " "Info: Found entity 1: altsyncram_ki31" {  } { { "db/altsyncram_ki31.tdf" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/db/altsyncram_ki31.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_ki31 signal_gene:si\|datarom:datarom_component\|altsyncram:altsyncram_component\|altsyncram_ki31:auto_generated " "Info: Elaborating entity \"altsyncram_ki31\" for hierarchy \"signal_gene:si\|datarom:datarom_component\|altsyncram:altsyncram_component\|altsyncram_ki31:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/quartus7.2/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "key.v 1 1 " "Warning: Using design file key.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 key " "Info: Found entity 1: key" {  } { { "key.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/key.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "key key:ke " "Info: Elaborating entity \"key\" for hierarchy \"key:ke\"" {  } { { "signal.v" "ke" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal.v" 15 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 key.v(20) " "Warning (10230): Verilog HDL assignment warning at key.v(20): truncated value with size 32 to match size of target (16)" {  } { { "key.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/key.v" 20 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "signal_gene:si\|Mult0 lpm_mult " "Info: Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"signal_gene:si\|Mult0\"" {  } { { "signal_gene.v" "Mult0" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 90 -1 0 } }  } 0 0 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "signal_gene:si\|Div0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"signal_gene:si\|Div0\"" {  } { { "signal_gene.v" "Div0" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 90 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus7.2/quartus/libraries/megafunctions/lpm_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/quartus7.2/quartus/libraries/megafunctions/lpm_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult " "Info: Found entity 1: lpm_mult" {  } { { "lpm_mult.tdf" "" { Text "e:/quartus7.2/quartus/libraries/megafunctions/lpm_mult.tdf" 284 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "signal_gene:si\|lpm_mult:Mult0 " "Info: Elaborated megafunction instantiation \"signal_gene:si\|lpm_mult:Mult0\"" {  } { { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 90 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_mk01.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_mk01.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_mk01 " "Info: Found entity 1: mult_mk01" {  } { { "db/mult_mk01.tdf" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/db/mult_mk01.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus7.2/quartus/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/quartus7.2/quartus/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "e:/quartus7.2/quartus/libraries/megafunctions/lpm_divide.tdf" 118 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "signal_gene:si\|lpm_divide:Div0 " "Info: Elaborated megafunction instantiation \"signal_gene:si\|lpm_divide:Div0\"" {  } { { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 90 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_g5m.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_g5m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_g5m " "Info: Found entity 1: lpm_divide_g5m" {  } { { "db/lpm_divide_g5m.tdf" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/db/lpm_divide_g5m.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_ckh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_ckh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_ckh " "Info: Found entity 1: sign_div_unsign_ckh" {  } { { "db/sign_div_unsign_ckh.tdf" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/db/sign_div_unsign_ckh.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}