signal.map.qmsg

yong VerilogHDL yu yan bianxie de pinlv fa sheng qi,shi yong ISE ruan jian da kai.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jun 07 13:50:00 2008 " "Info: Processing started: Sat Jun 07 13:50:00 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Signal -c signal " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Signal -c signal" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "oclk.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file oclk.v" { { "Info" "ISGN_ENTITY_NAME" "1 oclk " "Info: Found entity 1: oclk" {  } { { "oclk.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/oclk.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "signal.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file signal.v" { { "Info" "ISGN_ENTITY_NAME" "1 signal " "Info: Found entity 1: signal" {  } { { "signal.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal.v" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "signal_gene.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file signal_gene.v" { { "Info" "ISGN_ENTITY_NAME" "1 signal_gene " "Info: Found entity 1: signal_gene" {  } { { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "signal " "Info: Elaborating entity \"signal\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "oclk oclk:oc " "Info: Elaborating entity \"oclk\" for hierarchy \"oclk:oc\"" {  } { { "signal.v" "oc" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal.v" 13 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 oclk.v(12) " "Warning (10230): Verilog HDL assignment warning at oclk.v(12): truncated value with size 32 to match size of target (16)" {  } { { "oclk.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/oclk.v" 12 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "signal_gene signal_gene:si " "Info: Elaborating entity \"signal_gene\" for hierarchy \"signal_gene:si\"" {  } { { "signal.v" "si" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal.v" 14 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 signal_gene.v(26) " "Warning (10230): Verilog HDL assignment warning at signal_gene.v(26): truncated value with size 32 to match size of target (9)" {  } { { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 26 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 signal_gene.v(31) " "Warning (10230): Verilog HDL assignment warning at signal_gene.v(31): truncated value with size 32 to match size of target (8)" {  } { { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 31 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 signal_gene.v(45) " "Warning (10230): Verilog HDL assignment warning at signal_gene.v(45): truncated value with size 32 to match size of target (9)" {  } { { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 45 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 signal_gene.v(50) " "Warning (10230): Verilog HDL assignment warning at signal_gene.v(50): truncated value with size 32 to match size of target (8)" {  } { { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 50 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 signal_gene.v(65) " "Warning (10230): Verilog HDL assignment warning at signal_gene.v(65): truncated value with size 32 to match size of target (9)" {  } { { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 65 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 signal_gene.v(70) " "Warning (10230): Verilog HDL assignment warning at signal_gene.v(70): truncated value with size 32 to match size of target (8)" {  } { { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 70 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 signal_gene.v(85) " "Warning (10230): Verilog HDL assignment warning at signal_gene.v(85): truncated value with size 32 to match size of target (9)" {  } { { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 85 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 signal_gene.v(90) " "Warning (10230): Verilog HDL assignment warning at signal_gene.v(90): truncated value with size 32 to match size of target (8)" {  } { { "signal_gene.v" "" { Text "D:/Electronic/Quartus 7.2/EX/Signal/signal_gene.v" 90 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}